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high performance, low power, ism band fsk/gfsk/ook/msk/gmsk transceiver ic data sheet adf7023 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and r egistered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 C 2012 analog devices, inc. all rights reserved. features ultra low power , high performance transceiver f requency bands 862 mhz to 928 mhz 431 mhz to 464 mhz data rates supported 1 kbps to 300 kbps 2.2 v to 3.6 v power supply single - ended and differential pas low if receiver with programmable if bandwidths 100 khz, 150 khz, 200 khz, 300 khz receiver sensitivity (ber) ? 116 dbm at 1.0 kbps, 2fsk, gfsk ? 107.5 dbm at 38.4 kbps, 2fsk, gfsk ? 102.5 dbm at 150 kbps, gfsk, gmsk ? 100 dbm at 300 kbps, gfsk, gms k ? 104 dbm at 19.2 kbps, ook very l ow power consumption 12.8 ma in phy_rx mode (maximum front - end gain) 24.1 ma in phy_tx mode (10 dbm output, single - ended pa) 0.7 5 a in phy_sleep m ode ( 32 khz rc oscillator active) 1.2 8 a in phy_sleep mode (32 khz xtal oscillator active) 0.3 3 a in phy_sleep m ode (deep sleep mode 1) rf output power of ?20 dbm to +13.5 dbm (single - ended pa) rf output power of ?20 dbm to +10 dbm (differential pa) patented fast settling automatic frequency control (afc) digital received signal strength indication (rssi) integrated pll loop filter and tx/rx switch fast automatic vco calibration automatic synthesizer bandwidth optimization on - chip, low - power, custom 8 - bit processor radio control packet management smart wake mode packet management support highly flexible for a wide range of packet formats insertion /detection of preamble/ sync word /crc/address manchester and 8b / 10b data encoding and decoding data whitening smart wake mode current saving low power mode with autonomous receiver wake up, carrier sense, and packet reception downloadable firmware modules image rejection calibration, fully automated (patent pending) 128 - bit aes encryption/decryption with hardware acceleration and key sizes of 1 28 bits , 192 bits , and 256 bits reed solomon error correction with hardware acceleration 240 - byte packet buffer for tx/rx data efficient spi control interface with block read/write access integrated battery alarm and temperature sensor integrated rc and 32 .768 khz crystal oscillator on - chip , 8- bit adc 5 mm 5 mm, 32 - pin, lfcsp package a pplications smart metering ieee 802.15.4g wireless mbus home a utomation process and b uilding c ontrol wireless sensor networks (wsns) wireless healthcare
adf7023 data sheet rev. c | page 2 of 112 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 revision history ............................................................................... 3 functional block diagram .............................................................. 4 general description ......................................................................... 4 specifications ..................................................................................... 6 rf and synthesizer specifications .............................................. 6 transmitter specifications ........................................................... 7 re ceiver specifications ................................................................ 9 timing and digital specifications ............................................ 13 auxilary block specifications ................................................... 14 general specifications ............................................................... 15 timing specifications ................................................................ 16 absolute maximum ratings .......................................................... 17 esd caution ................................................................................ 17 pin configuration and function descriptions ........................... 18 typical performance characteristics ........................................... 20 terminology .................................................................................... 32 radio control .................................................................................. 33 radio states ................................................................................. 33 initialization ................................................................................ 35 commands .................................................................................. 35 automatic state transitions ...................................................... 37 state transition and command timing .................................. 38 packet mode .................................................................................... 43 preamble ...................................................................................... 43 sync word ................................................................................... 44 payload ......................................................................................... 45 crc .............................................................................................. 46 postamble ..................................................................................... 47 transmit packet timing ............................................................ 47 data whitening .......................................................................... 48 manchester encoding ................................................................ 48 8b/10b encoding ........................................................................ 48 sport mode ...................................................................................... 49 packet structure in sport mode ............................................... 49 sport mode in transmit ............................................................ 49 sport mode in receive ............................................................... 49 transmit bit latencies in sport mode ..................................... 49 interrupt generation ...................................................................... 52 interrupts in sport mode .......................................................... 53 adf7023 memory map ................................................................ 54 bbram ........................................................................................ 54 modem configuration ram (mcr) ...................................... 54 program rom ............................................................................ 54 program ram ............................................................................ 54 packet ram ................................................................................ 55 spi interface .................................................................................... 56 general characteristics ............................................................. 56 command access ....................................................................... 56 status word ................................................................................. 56 command queuing ................................................................... 57 memory acces s ........................................................................... 58 low power modes .......................................................................... 61 example low power modes ...................................................... 64 low power mode timing diagrams ........................................ 66 wuc setup ................................................................................. 67 firmware timer setup ............................................................... 69 calibrating the rc oscillator ................................................... 69 downloadable firmware modules ............................................... 71 writing a module to program ram ........................................ 71 image rejection calibration module ...................................... 71 reed solomon coding module ................................................ 71 aes encryption and decryption module ............................... 71 radio blocks .................................................................................... 73 frequency synthesizer ............................................................... 73 crystal oscillator ........................................................................ 74 modulation .................................................................................. 74 rf output stage .......................................................................... 74 pa/lna interface ....................................................................... 75 receive channel filter ............................................................... 75 image channel rejection .......................................................... 75 automatic gain control (agc) ............................................... 75 rssi .............................................................................................. 76 2fsk/gfsk/msk/gmsk demodulation ............................... 78 clock recovery ........................................................................... 80 ook demodulati on .................................................................. 80 recommended receiver settings for 2fsk/gfsk/msk/gmsk ......................................................... 81 recommended receiver settings for ook ............................ 82
data sheet adf7023 rev. c | page 3 of 112 peripheral features .......................................................................... 83 analog - to - digital converter ..................................................... 83 temperature sensor .................................................................... 83 te st dac ...................................................................................... 83 transmit test modes .................................................................. 83 silicon revision readback ......................................................... 83 applications information ............................................................... 84 application circuit ..................................................................... 84 host pro cessor interface ............................................................ 85 pa/lna matching ...................................................................... 85 command reference ...................................................................... 87 register maps .................................................................................. 88 bbram register description ................................................... 90 mc r register description ....................................................... 100 outline dimensions ...................................................................... 109 ordering guide ......................................................................... 109 revision history 7 /12 rev. b to rev. c changes to features section ............................................................ 1 changed 1.8 v to 2.2 v, general description section ................. 4 changed 1.8 v to 2.2 v, table 1 summary .................................... 6 changed 1.8 v to 2.2 v, table 2 ....................................................... 7 changes to table 3 ............................................................................ 9 changes to table 5 .......................................................................... 14 changes to v dd parameter, table 6 ............................................... 15 changes to timing specifications section ................................... 16 deleted t 1 from table 7 , figure 2 , and figure 3 ........................... 16 chang es to table 9 .......................................................................... 18 changes to figure 5 to figure 10 .................................................. 20 changes to figure 11 , figure 12 caption, figure 13 and figure 14 caption ............................................................................ 21 changes to figure 19 caption to figure 21 caption .................. 22 changes to figure 26 caption ....................................................... 23 changes to figure 34 cap tion ....................................................... 24 changes to figure 61 caption and figure 64 caption ............... 29 changes to figure 72 ...................................................................... 31 changes to phy_sleep section .................................................. 33 changes to initialization after application of power section, initialization after issuing the cmd_hw_reset command section, initialization on transitioning from phy_sleep (after cs is brought low) section, and initialization after a wuc timeout section ................................................................... 35 changes to cmd_ram_load_done ( 0 xc 7 ) section ......... 37 deleted cmd_sync ( 0 xa 2 ) section .......................................... 37 changes to state transition and command timing section .... 38 changes to table 11 and table 12 ................................................. 39 changes to addressing section ..................................................... 45 changes to example address check section, table 18 , and crc section .............................................................................................. 46 changes to figure 79 ...................................................................... 47 changes to figure 81 and figure 82 ............................................. 50 changes to figure 83 and figure 84 ............................................. 51 changes to cm d_finished description, table 24 ................. 53 changes to command access section ......................................... 56 changes to figure 97 ...................................................................... 63 changes to table 29 ........................................................................ 68 added calibrating the rc oscillator section, performing a fine calibration of the rc oscillator section, and performing a coarse calibration of the rc oscillator section ........................ 69 added figure 103 ; renumbered sequentially ............................. 70 changes to writing a module to program ram section .......... 71 changes to automatic pa ramp section equation and image channel rejection section ............................................................. 75 changes to temperature senso r section and table 43 .............. 83 changes to figure 110 .................................................................... 84 changes to figure 111 and figure 112 ......................................... 85 changes to support for external pa and lna control section and table 45 ..................................................................................... 86 changes to cmd_sync description column, table 46 .......... 87 changes to table 48 ........................................................................ 88 changes to tabl e 49 ........................................................................ 89 changes to synth_lut_control_ 1 description column, table 70 ............................................................................................. 93 changes to table 78 ........................................................................ 96 changes to table 79 ........................................................................ 97 changes to table 84 and table 86 ................................................. 98 changes to table 94 ........................................................................ 99 added table 95 , table 96 , and table 97 ; renumbered sequentially .................................................................................... 100 changes to t able 101 .................................................................... 101 added table 124 and table 125................................................... 105 3/11 rev. a to rev. b changes to rssi method 3 , formula ........................................... 72 change s to rssi method 4 , step 3 ................................................ 72 changes to rssi method 4 , step 5 formula and formula approximation ................................................................................ 73 add ed register 0x 361 to table 49 ................................................. 85 added table 129 , renumbered subsequent tables .................. 104 2/11 rev. 0 to rev. a changes to table 9, dguard description ................................ 18 changes to sport mode in receive section ................................. 47 changes to crystal oscillator section, typical crystal load capacitance tuning range value, and to table 31 ..................... 70 changes to rssi method 3 section .............................................. 72 changes to rssi method 4 section .............................................. 73 changes to table 41, 9.6 kbps and 1 kbps data rate setup values ..................................................................................... 78 changes to table 108 , adc_pd_n description ...................... 100 8 /10 revision 0 : initial version
adf7023 data sheet rev. c | page 4 of 112 f unctional block diag ram figure 1. general description the adf7023 is a very low pow er, high performance, highly integrated 2 fsk/gfsk/ook/msk/gmsk transceiver designed for operation in the 862 mhz to 928 mhz and 431 mhz to 464 mhz frequency bands, which cover the worldwide license - free ism bands at 433 mhz, 868 mhz , and 915 mhz. it is suitable for circuit applications that operate under the european etsi en300 - 220, the north american f cc (part 15), the chinese short - range wireless regulatory standards , or other similar regional standards . data rates from 1 kbps to 300 kbps are supported. the transmit rf synthesizer contains a vco and a low noise fractional - n pl l with an output channel f requency resolution of 400 hz. the vco operates at 2 or 4 , the fundamental frequency to reduce spurious emissions. the receive and transmit synthesizer bandwidths are automatically, and independently, c onfigured to achieve optimum phase n oise, modulation quality , and settling time. the transmitter output power is programmable from ?20 dbm to +13.5 dbm, with automatic pa ramping to meet transient spurious specifications. the part possesses both single- ended and differential pas, which allow s for tx antenna diversity. the receiver is exceptionally linear, achieving an ip3 specification of ?12.2 dbm and ?11.5 dbm at maximum gain and minimum gain, respectively, and an ip2 specification of 18.5 dbm and 27 dbm at maximum gain and minimum gain, re spectively. the receiver achieves an interference blocking specification of 66 db at 2 mhz offset and 74 db at 10 mhz offset. thus, the part is extremely resilient to the presence of interferers in spectrally noisy environments. the receiver features a n ovel, high speed , automatic frequency control (afc) loop, allowing the pll to find and correct any rf frequency errors in the recovered packet . a patent pending, image rejection calibration scheme is available through a program download. the algorithm does not require t he use of an external rf source nor does it require any user intervention once initiated. the results of the c alibration can be stored in non volatile memory for use on subsequent power - ups of the transceiver. the adf7023 operates with a power supply range of 2.2 v to 3.6 v and has very low power consumption in both tx and rx modes , enabling long lifetimes in batter y- operated systems while maintai ning excellent rf performance. the device can enter a low power sleep mode in which the configuration settings are retained in bbram. the adf7023 features an ultra low power, on - chip, communications processor. the communications processor, which is an 8- bit risc processor, performs the radio control, packet management , and smart wake mode (swm) functionality . the communications processor eases the processi ng burden of the companion processor by integrating the lower layers of a typical communication protocol stack. the communications pro cessor also permits the download and execution of a set of firmware modules that include image rejection (ir) calibration, aes encryption , and reed solomon coding. the communications proc essor provides a simple command - based radio control interface for the host processor . a single - byte command transitions the radio between states or performs a radio function. rssi/ logamp lna adcin_atb3 sclk mosi 1 gpio refers to pins 17, 18, 19, 20, 25, and 27. miso cs irq_gp3 rfio_1p rfio_1n rfo2 spi irq ctrl fsk ask demod cdr afc agc 4kb rom mac 256 byte packet ram 2kb ram 8-bit risc processor bias 26mhz osc ldo4 ldo3 ldo2 ldo1 wake-up control timer unit 64 byte bbram temp sensor battery monitor clock divider gpio test dac analog test pa ramp profile pa mux 8-bit adc loop filter charge pump pfd 26mhz osc divider - modulator gaussian filter f dev 32khz rcosc 32khz osc pa adf7023 256 byte mcr ram gpio 1 divider 08291-001 xosc26n xosc26p xosc32kp_gp5_atb1 xosc32kn_atb2 rbias cregrfx cregvco cregsynth cregdigx
data sheet adf7023 rev. c | page 5 of 112 the communications processor provides support for generic packet format s . the packet format is highly flexible and fully progra mmable, thereby ensuring its compatib il ity with proprietary packet profiles. in transmit mod e, the commun - ications processor can be configured to add preamble, sync word , and crc to the payload data stored in packet ram. in receive mode , the communications processor can detect and interrupt the host processor on reception of preamble, sync word, address , and crc and store the received payload to packet ram. the adf7023 u ses an efficient interrupt system comprising mac level i nterrupts and phy level interrupts that can be individually set. the payload data plus the 16 - bit crc can be encoded/decoded using manchester or 8b/10b encoding. alter natively, data whitening and de whitening can be applied. the smart wake mode (swm) allows the adf7023 to wake up autonomously from sleep using the internal wake - up timer without intervention from the host processor. after wake - up , the adf7023 is controlled by the communications processor. this functionality allows carrier sense, packet sniffing , and packe t reception while the host processor is in sleep, thereby reducing overall system current consumption. the smart wake mode can wake the host processor on an interrupt condition. these interrupt conditions can be co n figured to include the reception of valid preamble, s ync word, crc, or address match. wa ke - up from sleep mode can also be triggered by the host processor . for systems requiring very accurate wake - up timing , a 32 khz oscillato r can be used to drive the wake - up timer. alternatively, the internal rc oscillator can be used, which gives lower current consumption in sleep. the adf7023 features an a dvanced e ncryption s tandard (aes) engine with hardware acceleration that provides 128- bit block encryption and decryption with key sizes of 128 bits , 192 bits, and 256 bits. both electronic code b ook (ecb) and cipher block c haining mode 1 (cbc mode 1) are supported. the aes engine can be used to encrypt/decrypt packet data and can be used as a stand alone engine for encrypt ion/decryption by the host process or. the aes engine is enabled on the adf702 3 by downloading the aes software module to program ram . the aes software module is available from analog devices , inc . an on - chip , 8- bit adc provides readback of an external analog input, the rssi signal, or an i ntegrated temperature sensor. an integrated battery voltage monitor raises an interrupt flag to the host processor whenever the battery voltage drops below a us er - defined threshold.
adf7023 data sheet rev. c | page 6 of 112 specifications v dd = vddbat1 = vddbat2 = 2.2 v to 3.6 v, gnd = 0 v, t a = t min to t max , unless otherwise noted. typical specifications are at v dd = 3 v, t a = 25c. rf and synthesizer s pecifications table 1. parameter min typ max unit test conditions rf characteristics frequency ranges 862 928 mhz 431 464 mhz phase - locked loop channel f req uency r esolution 396.7 hz phase noise (in - band) ?88 dbc/hz 10 khz o ffset, pa output power = 10 dbm, rf = 868 mhz phase noise at o ffset of 1 mhz ? 126 dbc/hz pa output power = 10 dbm, rf frequency = 868 mhz 2 mhz ? 131 dbc/hz pa output power = 10 dbm, rf frequency = 868 mhz 10 mhz ? 142 dbc/hz pa output power = 10 dbm, rf frequency = 868 mhz vco calibration time 142 s synthesizer settling time 56 s frequency synthesizer settles to within 5 ppm of the target frequency within this time following the vco calibration , transmit, and receive, 2fsk/gfsk/ msk/gmsk crystal oscillator crystal f requency 26 mhz parallel load resonant crystal recommended load c apacitance 7 18 pf maximum crystal esr 1800 26 mhz crystal with 18 pf load capacitance p in capacitance 2.1 pf capacitance for xosc26p and xosc26n start - up time 310 s 26 mhz crystal with 7 pf load capacitance 388 s 26 mhz crystal with 18 pf load capacitance spurious emissions integer boundary spurious 910.1 mhz ? 39 dbc u sing 130 kh z synthesizer bandwidth, integer boundary spur at 910 mhz ( 26 mhz 35) , inside synthesizer loop bandwidth 911.0 mhz ? 79 dbc u sing 130 kh z synthesizer bandwidth, integer boundary spur at 910 mhz ( 26 mhz 35) , outside synthesizer loop bandwidth reference spurious 868 mhz/915 mhz ? 80 dbc u sing 130 k hz synthesizer bandwidth and u sing 92 khz synthesizer bandwidth (default for phy_rx) clock - related spur level ? 60 dbc measured in a span of 350 mhz for synthesizer ban d width = 92 khz, rf f requency = 868.95 mhz, pa output power = 10 dbm, v dd = 3.6 v, single - ended pa used
data sheet adf7023 rev. c | page 7 of 112 transmitter specifications table 2. parameter min typ max unit test conditions data rate 2fsk/gfsk /msk/gmsk 1 300 kbps ook 2.4 19.2 k bps manchester encoding enabled (manchester chip rate = 2 data rate) data rate resolution 100 bps modulation error rate (mer) rf f requency = 928 mhz, gfsk 10 kbps to 49. 5 kbps 25. 4 db modulation index = 1 49. 6 kbps to 129. 5 kbps 25.3 db modulation index = 1 129. 6 kbps to 179. 1 kbps 23.9 db modulation index = 0.5 179. 2 kbps to 239.9 kbps 23.3 db modulation index = 0.5 240 kbps to 300 kbps 23 db modulation index = 0.5 modulation 2fsk/gfsk /msk/gmsk frequency deviation 0.1 409.5 khz deviation frequency resolution 100 hz gaussian filter bt 0.5 nonp rogrammable ook pa off feedthrough ? 94 dbm vco frequency pulling 30 khz rms data rate = 19.2 kbps (38.4 kcps manchest er encoded), pa output = 10 dbm, pa ramp rate = 64 codes/bit single - ended pa maximum power 1 13.5 dbm programmable, separate pa and lna match 2 minimum power ? 20 dbm tr ansmit power variation vs. t emperature 0.5 db from ? 40c to +85 c , rf f requency = 868 mhz transmit power variation vs. v dd 1 db from 2.2 v to 3.6 v, rf frequency = 868 mhz transmit power flatness 1 db from 902 mhz to 928 mhz and 863 mhz to 870 mhz programmable step size ?20 dbm to +1 3.5 dbm 0.5 db p rogrammable in 63 steps differ en tial pa maximum power 1 10 dbm programmable minimum power ? 20 dbm tr ansmit power variation vs. t emperature 1 db from ? 40c to +85 c , rf f requency = 868 mhz transmit power variation vs. v dd 2 db from 2.2 v to 3.6 v, rf frequency = 868 mhz transmit power flatness 1 db from 863 mhz to 870 mhz programmable step size ?20 dbm to +1 0 dbm 0.5 db p rogrammable in 63 steps harmonics 868 mhz, u nfiltered conductive , pa output power = 10 dbm single -e nded pa second harmonic ? 15.1 dbc third harmonic ? 29.3 dbc all other harmonics ? 47.6 dbc differential pa second harmonic ? 23.2 dbc third harmonic ?2 5.2 dbc all other harmonics ? 24.2 dbc
adf7023 data sheet rev. c | page 8 of 112 parameter min typ max unit test conditions optimum pa load impedance single -e nded pa, in transmit m ode f rf = 915 mhz 50 .8 + j 10 .2 f rf = 868 mhz 45 .5 + j1 2.1 f rf = 433 mhz 46.8 + j19.9 single -e nded pa, in receive m ode f rf = 915 mhz 9.4 ? j124 f rf = 868 mhz 9.5 ? j130.6 f rf = 433 mhz 11.9 ? j260.1 differential pa, in transmit m ode load impedance between rfio_1p and rfio_1n to ensure maximum output power f rf = 915 mhz 20 .5 + j 36 .4 f rf = 868 mhz 24 .7 + j3 6. 5 f rf = 433 mhz 55.6 + j 81.5 1 measured as the maximum unmodulated power. 2 a combi ned single - ended pa and lna match can reduce the maximum achievable output power by up to 1 db .
data sheet adf7023 rev. c | page 9 of 112 receiver specificati ons table 3. parameter min typ max unit test conditions 2fsk/gfsk /msk/gmsk input sensitiv i t y, bit error r ate (ber) at ber = 1e ? 3, rf f requency = 433 mhz, 868 mhz, 915 mhz , lna and pa matched separately 1 1.0 kbps ? 116 dbm frequency d eviation = 4.8 khz, if filter b andwidth = 100 khz 10 kbps ? 111 dbm frequency d eviation = 9.6 khz, if f ilter b andwidth = 100 khz 38.4 kbps ? 107.5 dbm frequency d eviation = 20 khz, if f ilter b andwidth = 100 khz 50 kbps ?106.5 dbm frequency deviation = 12.5 khz, if filter bandwidth = 100 khz 100 kbps ?105 dbm frequency deviation = 25 khz, if filter bandwidth = 100 khz 150 kbps ?104 dbm frequency deviation = 37.5 khz, if filter bandwidth = 150 khz 200 kbps ?103 dbm frequency deviation = 50 khz, if filter bandwidth = 200 khz 300 kbps ?100.5 dbm frequency deviation = 75 khz, if filter bandwidth = 300 khz 2fsk/gfsk/msk/gmsk input sensitiv i t y, packet error rate (per) at per = 1%, rf frequency = 433 mhz, 868 mhz, 915 mhz , lna and pa matched separately 1 , packet length = 128 bits, packet mode 1.0 kbps ?115.5 dbm frequency deviation = 4.8 khz, if filter bandwidth = 100 khz 9.6 kbps ?110.6 dbm frequency deviation = 9.6 khz, if filter bandwidth = 100 khz 38.4 kbps ?106 dbm frequency deviation = 20 khz, if filter bandwidth = 100 khz 50 kbps ?104.3 dbm frequency deviation = 12.5 khz, if filter bandwidth = 100 khz 100 kbps ?10 2.6 dbm frequency deviation = 25 khz, if filter bandwidth = 100 khz 150 kbps ?101 dbm frequency deviation = 37.5 khz, if filter bandwidth = 150 khz 200 kbps ?99 .1 dbm frequency deviation = 50 khz, if filter bandwidth = 200 khz 300 kbps ?97.9 dbm frequency deviation = 75 khz, if filter bandwidth = 300 khz ook input sensitivity , packet error rate (per) at per = 1%, rf frequency = 433 mhz, 868 mhz, 915 mhz, lna and pa matched separately 1 , packet length = 128 bits, packet mode, if filter bandwidth = 100 khz 19.2 kbps (38.4 kcps, manchester e ncoded) ?104 .7 dbm 2.4 kbps (4.8 kcps, manchester e ncoded) ? 109.7 dbm lna and mixer, input ip3 receiver lo f requency (f lo ) = 914.8 mhz , f source1 = f lo + 0.4 mhz, f source2 = f lo + 0.7 mhz minimum lna g ain ?11.5 dbm maximum lna g ain ?12.2 dbm lna and mixer, input ip2 receiver lo f requency (f lo ) = 920.8 mhz , f source1 = f lo + 1.1 mhz, f source2 = f lo + 1.3 mhz max lna g ain, max mixer g ain 18.5 dbm min lna gain, min mixer g ain 27 dbm
adf7023 data sheet rev. c | page 10 of 112 parameter min typ max unit test conditions lna and mixer, 1 db compression point rf f requency = 915 mhz max lna g ain , max mixer g ain ?21.9 dbm min lna gain, min mixer g ain ? 21 dbm adjacent channel rejection cw in t erferer wanted signal 3 db above the input sensitivity level (ber = 10 ?3 ), cw interferer power level increased until ber = 10 ?3 , i mage calibrated 200 khz channel spacing 38 db if bw = 100 khz, wanted signal: f dev = 12.5 khz, dr = 50 kbps 300 khz channel spacing 39 db if bw = 100 khz, wanted signal: f dev = 25 khz, dr = 100 kbps 38 db if bw = 150 khz, wanted signal: f dev = 37.5 khz, dr = 150 kbps 400 khz channel spacing 40 db if bw = 200 khz, wanted signal: f dev = 50 khz, dr = 200 kbps 600 khz channel spacing 41 db if bw = 300 khz, wanted signal: f dev = 75 khz, dr = 300 kbps modulated interferer wanted signal 3 db above the input sensitivity level (ber = 10 ?3 ), m odulated interferer with the same mo dulation as the wanted signal; interferer power level increased until ber = 10 ?3 , image calibrated 200 khz channel spacing 38 db if bw = 100 khz, wanted signal: f dev = 12.5 khz, dr = 50 kbps 300 khz channel spacing 36 db if bw = 100 khz, wanted signal: f dev = 25 khz, dr = 100 kbps 300 khz channel spacing 36 db if bw = 150 khz, wanted signal: f dev = 37.5 khz, dr = 150 kbps 400 khz channel spacing 34 db if bw = 200 khz, wanted signal: f dev = 50 khz, dr = 200 kbps 600 khz channel spacing 35 db if bw = 300 khz, wanted signal: f dev = 75 khz, dr = 300 kbps co - channel rejection ?4 db desired signal 10 db above the input sensitivity level (ber = 10 ?3 ), data rate = 38.4 kbps, frequency deviation = 20 khz , rf f requency = 868 mhz blocking desired signal 3 db above the input sensitivity level (ber = 10 ?3 ) of ?107.5 dbm (d ata r ate = 38.4 kbps), modulated interferer power level increased until ber = 10 ?3 ( see the typical performance characteristics section for blocking at other offsets and if bandwidths) rf frequency = 433 mhz 2 mhz 68 db 10 mhz 76 db rf frequency = 868 mhz 2 mhz 66 db 10 mhz 7 4 db rf frequency = 915 mhz 2 mhz 66 db 10 mhz 74 db
data sheet adf7023 rev. c | page 11 of 112 parameter min typ max unit test conditions blocking, etsi en 300 220 measurement procedure as per etsi en 300 220 -1 v2.3.1; desired signal 3 db above the etsi en 300 220 reference sensitivity level of ?99 dbm, if bandwidth = 100 khz, data rate = 38.4 kbps, unmodulated interferer; see the typical performance characteristics section for blocking at other offsets and if bandwidths, rf f requency = 868 mhz 2 mhz ?28 dbm 10 mhz ?20.5 dbm wideband interference rejection 75 db rf frequency = 868 mhz, swept from 10 mhz to 100 mhz either side of the rf frequency image channel attenuation measured as image attenuation at the if filter output, carrier wave interferer at 400 khz below the channel frequency, 100 khz if filter bandwidth 868 mhz, 915 mhz 36 /45 db uncalibrated/calibrated 433 mhz 40 /54 db uncalibrated/calibrated afc accuracy 1 khz maximum pull - in range achievable pull - in range dependent on discriminator bandwidth and modulation 300 khz if filter bandwidth 150 khz 200 khz if filter bandwidth 100 khz 150 khz if filter bandwidth 75 khz 100 khz if filter bandwidth 50 khz p reamble length minimum number of preamble bits to ensure the minimum packet error rate across the full input power range afc off, agc lock on sync word detection 38.4 kbps 8 bits 300 kbps 24 bits afc on, afc and agc lock on preamble detection 9.6 kbps 44 bits 38.4 kbps 44 bits 50 kbps 50 bits 100 kbps 52 bits 150 kbps 54 bits 200 kbps 58 bits 300 kbps 64 bits afc on, afc and agc lock on sync word detection 38.4 kbps 14 bits 300 kbps 32 bits rssi range at input ?97 to ?26 dbm linearity 2 db absolute accuracy 3 db saturation (maximum input level) 2fsk/gfsk/msk/gmsk 12 dbm ook ? 13 dbm ook modulation depth = 20 db 10 dbm ook modulation depth = 60 db
adf7023 data sheet rev. c | page 12 of 112 parameter min typ max unit test conditions lna input impedance receive mode f rf = 915 mhz 75.9 ? j32.3 f rf = 868 mhz 78.0 ? j32.4 f rf = 433 mhz 95.5 ? j23.9 transmit mode f rf = 915 mhz 7.6 + j9.2 f rf = 868 mhz 7.7 + j8.6 f rf = 433 mhz 7.9 + j4.6 rx spurious emissions 2 maximum <1 ghz ? 66 dbm at antenna input, unfiltered conductive maximum >1 ghz ? 62 dbm at antenna input, unfiltered conductive 1 sensitivity for combined matching network case is typically 1 db less than separate matching networks. 2 follow the matching and layout guidelines to achieve the relevant fcc/etsi specifications .
adf7023 rev. c | page 13 of 112 timing and digital specific ations table 4. parameter min typ max unit test conditions rx and tx timing parameters see the state transition and command timing section for more details phy_on to phy_rx (on cmd_phy_rx) 300 s i ncludes vco calibration and synthesizer settling phy_on to phy_tx (on cmd_phy_tx) 296 s i ncludes vco calibration and synthesizer settling, does no t include pa ramp -up logic inputs input high voltage, v inh 0.7 v dd v input low voltage, v inl 0.2 v dd v input current, i inh /i inl 1 a input capacitance, c in 10 pf logic outputs output high voltage, v oh v dd ? 0.4 v i oh = 500 a output low voltage, v ol 0.4 v i ol = 500 a gpio rise/fall 5 ns gpio load 10 pf maximum output current 5 ma atb outputs used for external pa and lna control adcin_atb3 and atb4 output high voltage, v oh 1.8 v output low voltage, v ol 0.1 v maximum output current 0.5 ma xosc32kp_gp5_atb1 and xosc32kn_atb2 output high voltage, v oh v dd v output low voltage, v ol 0.1 v maximum output current 5 ma
adf7023 data sheet rev. c | page 14 of 112 auxilary block speci fications table 5. parameter min typ max unit test conditions 32 khz rc oscillator frequency 32.768 khz a fter calibration frequency a ccuracy 1.5 % a fter calibration at 25c frequency drift temperature coefficient 0.14 %/c voltage coefficient 4 %/v calibration time 1 .25 ms 32 khz xtal oscillator frequency 32.768 khz start -u p t ime 630 ms 32.768 khz crystal with 7 pf load capacitance wake up controller (wuc) hardware timer wake -u p p eriod 61 10 ? 6 1.31 10 5 sec firmware timer wake -u p p eriod 1 2 16 hardware periods f irmware counter counts of the number of hardware wake - ups , resolution of 16 bits adc resolution 8 b its dnl 1 lsb v dd f rom 2.2 v to 3.6 v, t a = 25c inl 1 lsb v dd f rom 2.2 v to 3.6 v, t a = 25c conversion t ime 1 s input capacitance 12.4 pf battery monitor absolute accuracy 45 mv alarm voltage set point 1.7 2.7 v alarm voltage step size 62 mv 5- bit resolution start - up time 100 s current consumption 30 a when enabled temperature sensor range ?40 +85 c resolution 0.3 c with averaging accuracy of temperature readback +7/ ?4 c over temperature range ?40c to +85c (calibrated at +25c)
data sheet adf7023 rev. c | page 15 of 112 general specificatio ns table 6. parameter min typ max unit test conditions temperature range, t a ?40 +85 c voltage supply v dd 2.2 3.6 v applied to vddbat1 and vddbat2 tran s mit cu rr ent consumption in the phy_tx state, single - ended pa matched to 50 , differential pa matched to 10 0 , s eparat e single - ended pa and lna match , c ombined differential pa and lna match single -e nded pa, 433 mhz ?10 dbm 8. 7 ma 0 dbm 12.2 ma 10 dbm 2 3.3 ma 13.5 dbm 32.1 ma differential pa, 433 mhz ?10 dbm 7. 9 ma 0 dbm 11 ma 5 dbm 15 ma 10 dbm 22. 6 ma single -e nded pa, 868 mhz /915 mhz ?10 dbm 10.3 ma 0 dbm 13.3 ma 10 dbm 24.1 ma 13.5 dbm 32.1 ma differential pa, 868 mhz /915 mhz ?10 dbm 9.3 ma 0 dbm 12 ma 5 dbm 16.7 ma 10 dbm 28 ma power modes phy_sleep (deep sleep mo de 2) 0.1 8 a sleep mode, wake - up conf iguration values (bbram) not retained phy_sleep (deep sleep mo de 1) 0.3 3 a sleep mode, wake - up configuration values (bbram) retained phy_sleep (rco wake mode) 0. 75 a wuc active, rc o scillator running, wake - up configuration values retained (bbram) phy_sleep (xto wake mode) 1.2 8 a wuc active, 32 khz crystal running, wake - up configuration values retained (bbram) phy_off 1 ma device in phy_ off state , 26 mhz oscillator running, digital and synthesizer regulators active, all register values retained phy_on 1 ma device in phy_ on state , 26 mhz oscillator running, digital, synthesizer, vco , and rf regulators active, baseband filter calibration performed, all register values retained phy_rx 12.8 ma device in phy_rx state smart wake mode average current consumption 21.78 a autonomous reception every 1 s ec , with receive dwell time of 1.25 ms, using rc oscillator , d ata rate = 38.4 kbps 11.75 a autonomous reception every 1 s ec , with receive dwell time of 0.5 ms, using rc oscillator, d ata rate = 300 kbps
adf7023 data sheet rev. c | page 16 of 112 timing specifications v dd = vddbat1 = vddbat2 = 2.2 v to 3.6 v , v gnd = gnd = 0 v, t a = t min to t ma x , unless otherwise noted. table 7 . spi interface timing parameter limit unit test conditions/comments t 2 85 ns min cs low to sclk setup time t 3 85 ns min sclk high time t 4 85 ns min sclk low time t 5 170 ns min sclk period t 6 10 ns max sclk falling edge to miso delay t 7 5 ns min mosi to sclk rising edge setup time t 8 5 ns min mosi to sclk rising edge hold time t 9 85 ns min sclk falling edge to cs hold time t 11 270 ns min cs high time t 12 310 s typ cs low to miso high wake - up time, 26 mhz crystal with 7 pf load capacitance, t a = 25c t 13 20 ns max sclk rise time t 14 20 ns max sclk fall time timing diagrams figure 2 spi interface t iming figure 3 phy_sleep to spi ready state t iming ( spi r eady t12 a fter f alling e dge of cs ) t 11 t 9 t 4 t 5 t 13 t 3 t 2 t 14 t 6 t 8 t 7 cs sclk miso mosi 7 7 6 5 4 3 2 1 0 7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 0 x bit 7 08291-002 spi s ta te cs sclk miso sleep w ake u p spi read y x 012345 t 9 67 t 6 t 12 08291-003
data sheet adf7023 rev. c | page 17 of 112 absolute maximum rat ings t a = 25c, unless otherwise noted. table 8. parameter rating v ddbat1, vddbat2 to gnd ? 0.3 v to +3.9 6 v operating temperature range industrial ? 40c to +85c storage temperature range ? 65c to +125c maximum junction temperature 150c lfcsp ja thermal impedance 26c/w reflow soldering peak temperature 260c time at peak temperature 40 sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. connect the exposed paddle of the lfcsp package to ground. this device is a high performance , rf integrated circuit with an esd rating of <2 kv; it is esd sensitive. proper precautions should be taken for handling and assembly. esd caution
adf7023 data sheet rev. c | page 18 of 112 pin configuration and function descripti ons figure 4 . pin configuration table 9. pin function descriptions pin no. mnemonic function 1 cregrf 1 regulator voltage for rf. a 220 nf capacitor should be placed between this pin and ground for regulator stability and noise rejection. 2 rbias external b ias r esistor . a 36 k resistor with 2% tolerance should be used. 3 cregrf2 regu lator v oltage for rf. a 22 0 nf capacitor should be placed between this pin and ground for regulator stability and noise rejection. 4 rfio_1p lna positive input in r eceive m ode . pa p ositive o utput in transmit mode with differential pa. 5 rfio_1n lna n egative input in r eceive m ode . pa n egative o utput in transmit mode with differential pa. 6 rfo2 single -e nded pa o utput . 7 vddbat2 power supply p in t wo. decoupling capacitors to the ground plane should be placed as close as possible to this pin. 8 nc no connect . 9 cregvco regu lator v oltage for the vco. a 22 0 nf capacitor should be placed between this pin and ground for regulator stability and noise rejection. 10 vcoguard guard/ s creen for vco. this pin should be connected to pin 9. 11 cregsynth regu lator voltage for the s ynthesizer. a 22 0 nf capacitor should be placed between this pin and ground for regulator stability and noise rejection. 12 cwakeup external capacitor for wake - up c ontrol . a 150 nf capacitor should be placed between this pin and ground. 13 xosc26p the 26 mhz reference crystal should be connected between this pin and xosc26n. if an external ref erence is connected to xosc26n , this pin should be left open circuited. 14 xosc26n the 26 mhz reference crystal should be connected between this pin and xosc26p. alternatively, an external 26 mhz reference signal can be ac - coupled to this pin. 15 dguard internal g uard/ scr een for the digital c ircuitry. connect t his pin t o pin 16, cregdig1 . 16 cregdig1 regu lator v oltage for d igital s ection of the c hip. a 22 0 nf capacitor should be placed between this pin and ground for regulator stability and noise rejection. 17 gp0 digital gpio p in 0 . 18 gp1 digital gpio p in 1 . 19 gp2 digital gpio p in 2 . 20 irq_gp3 interrupt request, digital gpio t est p in 3. 21 miso serial p ort master in/ slave out . notes 1. nc = no connec t. 2. connect exposed p ad t o gnd. 24 cs 23 mosi 22 sclk 21 miso 20 irq_gp3 19 gp2 18 gp1 17 gp0 1 2 3 4 5 6 7 8 cregrf1 rbias cregrf2 rfio_1 p rfio_1n rfo2 vddb a t2 nc 9 10 11 12 13 14 15 16 cregvco vcoguard cregsynth cw akeu p xosc26 p xosc26n dguard cregdig1 32 31 30 29 28 27 26 25 adcvref a tb4 adcin_ a tb3 vddb a t1 xosc32kn_ a tb2 xosc32kp_gp5_ a tb1 cregdig2 gp4 top view (not to scale) adf7023 ep ad 08291-004
data sheet adf7023 rev. c | page 19 of 112 pin no. mnemonic function 22 sclk serial p ort clock . 23 mosi serial p ort master out / slave in . 24 cs chip s elect (a ctive l ow). a pull -up resistor of 100 k to v dd is recommended to prevent the host processor from inadvertently waking the adf702 3 from sleep. 25 gp4 digital gpio t est p in 4. 26 cregdig2 regu lator v oltage for d igital section of the c hip. a 22 0 nf capacitor should be placed between this pin and ground for regulator stability and noise rejection. 27 xosc32kp_gp5_atb1 digital gpio t est p in 5. a 32 khz watch crystal can be connected between this pin and xosc32kn_atb2 . analog t est p in 1. 28 xosc32kn_atb2 a 32 khz watch crystal can be connected between this pin and xosc32kp_gp5_atb1 . analog test p in 2. 29 vddbat1 digital power supply p in o ne. decoupling capacitors to the ground plane should be placed as close as possible to this pin . 30 adcin_atb3 analog - to - digital converter input. can be configured as an external pa enable signal. analog test pin 3. 31 atb4 analog t est p in 4. can be configured as an external lna enable signal. 32 adcvref adc reference o utput. a 22 0 nf capacitor should be placed between th is pin and ground for adequate noise rejection. epad gnd exposed p ackage p addle. connect to gnd.
adf7023 data sheet rev. c | page 20 of 112 typical performance characteristics figure 5. single - ended pa at 433 mhz: output power vs. pa_level_mcr s etting, temperature , and v dd figure 6. single - ended pa at 433 mhz: supply current vs. output power, temperature , and v dd (minimum recommended v dd = 2.2 v, 1.8 v operation shown for robustness) figure 7. single - ended pa at 868 mhz: output power vs. pa_level_mcr s etting, temperature , and v dd figure 8. single - ended pa at 868 mhz: supply current vs. output power, temperature , and v dd figure 9 . single- ended pa at 915 mhz: output power vs. pa_level_mcr s etting, temperature , and v dd figure 10 . sin gle - ended pa at 915 mhz: supply current vs. output power, temperature , and v dd (minimum recommended v dd = 2.2 v, 1.8 v operation shown for robustness) ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 output power (dbm) p a_level_mcr ?40c, 3.6v ?40c, 3.0v ?40c, 2.4v +25c, 3.6v +25c, 3.0v +25c, 2.4v +85c, 3.6v +85c, 3.0v +85c, 2.4v 08291-164 0 5 10 15 20 25 30 35 40 ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 supply current (ma) pa output power (dbm) ?40c, 3.6v ?40c, 1.8v +25c, 3.6v +25c, 1.8v +85c, 3.6v +85c, 1.8v 08291-165 ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 output power (dbm) p a_level_mcr ?40c, 3.6v ?40c, 3.0v ?40c, 2.4v +25c, 3.6v +25c, 3.0v +25c, 2.4v +85c, 3.6v +85c, 3.0v +85c, 2.4v 08291-166 0 5 10 15 20 25 30 35 ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 supply current (ma) output power (dbm) ?40c, 3.6v ?40c, 1.8v +25c, 3.6v +25c, 1.8v +85c, 3.6v +85c, 1.8v 08291-167 ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 output power (dbm) p a_level_mcr ?40c, 3.6v ?40c, 3.0v ?40c, 2.4v +25c, 3.6v +25c, 3.0v +25c, 2.4v +85c, 3.6v +85c, 3.0v +85c, 2.4v 08291-168 0 5 10 15 20 25 30 35 40 ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 supply current (ma) output power (dbm) ?40c, 3.6v ?40c, 1.8v +25c, 3.6v +25c, 1.8v +85c, 3.6v +85c, 1.8v 08291-169
data sheet adf7023 rev. c | page 21 of 112 figure 11 . differential pa at 433 mhz: output power vs. pa_level_mcr s etting, temperature , and v dd (minimum recommended v dd = 2.2 v, 1.8 v operation shown for robustness) figure 12 . differential pa at 433 mhz: supply current vs. output power, temperature , and v dd (minimum recommended v dd = 2.2 v, 1.8 v operation sho wn for robustness) figure 13 . differential pa at 915 mhz: output power vs. pa_level_mcr s etting, temperature , and v dd (minimum recommended v dd = 2.2 v, 1.8 v operation shown for robustness) figure 14 . differential pa at 915 mhz: supply current vs. output power, temperature , and v dd (minimum recommended v dd = 2.2 v, 1.8 v operation shown for robustness) figure 15 . pa ramp - up at data rate =38.4 kbps for each pa_ramp s ettin g , differential pa figure 16 . pa ramp -d own at data r ate =38.4 kbps f or each pa_ramp s etting , differential pa ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 14 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 output power (dbm) p a_level_mcr ?4 0 c, 3.6v ?4 0 c, 3.0v ?4 0 c, 2.4v ?4 0 c, 1. 8v +8 5 c, 3.6v +8 5 c, 3.0v +8 5 c, 2.4v +8 5 c, 1.8v +2 5 c, 3.6v +2 5 c, 3.0v +2 5 c, 2.4v +2 5 c, 1.8v 08291-207 6 8 10 12 14 16 18 20 22 24 26 28 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 supply current (ma) output power (dbm) ?40c, 3.6v ?40c, 1.8v +85c, 3.6v +85c, 1.8v 08291-208 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 output power (dbm) p a_level_mcr ?4 0 c, 3.6v ?4 0 c, 3.0v ?4 0 c, 2.4v ?4 0 c, 1.8v +8 5 c, 3.6v +8 5 c, 3.0v +8 5 c, 2.4v +8 5 c, 1.8v +2 5 c, 3.6v +2 5 c, 3.0v +2 5 c, 2.4v +2 5 c, 1.8v 08291-209 6 8 10 12 14 16 18 20 22 24 26 28 30 32 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 supply current (ma) output power (dbm) ?40c, 3.6v ?40c, 1.8v +85c, 3.6v +85c, 1.8v 08291-210 ?60 ?50 ?40 ?30 ?20 ?10 0 10 0 50 100 150 200 250 300 350 400 450 500 pa output power (dbm) time (s) pa ram p = 1 pa ram p = 2 pa ram p = 3 pa ram p = 4 pa ram p = 5 pa ram p = 6 pa ram p = 7 08291-211 ?60 ?50 ?40 ?30 ?20 ?10 0 10 0 50 100 150 200 250 300 350 400 450 500 pa output power (dbm) time (s) pa ram p = 1 pa ram p = 2 pa ram p = 3 pa ram p = 4 pa ram p = 5 pa ram p = 6 pa ram p = 7 08291-212
adf7023 data sheet rev. c | page 22 of 112 rev figure 17 . pa r amp - up at data rate =300 kbps for each pa_ramp s etting , differential pa figure 18 . pa r amp- down at data r ate =300 kbps for each pa_ramp s etting , differential pa figure 19 . transmit spectrum at 868 mhz, fsk, data rate = 38.4 kbps, frequency deviation = 20 khz (minimum recommended v dd = 2.2 v, 1.8 v operation shown for robustness) figure 20 . transmit spectrum at 868 mhz, gfsk, data r ate = 38.4 kbps, frequency deviation = 20 khz (minimum recommended v dd = 2.2 v, 1.8 v operation shown for robustness) figure 21 . transmit spectrum at 928 mhz, gfsk, data r ate = 300 kbps, frequency deviation = 75 khz (minimum recommended v dd = 2.2 v, 1.8 v operation shown for robustness) figure 22 . transmit eye at 868 mhz, gfsk, data r ate = 38.4 kbps, frequency deviation = 21 khz ?60 ?50 ?40 ?30 ?20 ?10 0 10 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 pa output power (dbm) time (s) pa ram p = 4 pa ram p = 5 pa ram p = 6 pa ram p = 7 08291-213 ?60 ?50 ?40 ?30 ?20 ?10 0 10 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 pa output power (dbm) time (s) pa ram p = 4 pa ram p = 5 pa ram p = 6 pa ram p = 7 08291-214 ?60 ?50 ?40 ?30 ?20 ?10 0 10 ?250 ?200 ?150 ?100 ?50 0 50 100 150 200 250 frequenc y offset (khz) power (dbm) 3.6v, ?4 0 c 1.8v, ?4 0 c 3.6v, +8 5 c 1.8v, +8 5 c 08291-040 ?60 ?50 ?40 ?30 ?20 ?10 0 10 ?250 ?200 ?150 ?100 ?50 0 50 100 150 200 250 frequenc y offset (khz) power (dbm) 3.6v, ?4 0 c 1.8v, ?4 0 c 3.6v, +8 5 c 1.8v, +8 5 c 08291-041 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 ?1000 ?900 ?800 ?700 ?600 ?500 ?400 ?300 ?200 ?100 0 100 200 300 400 500 600 700 800 900 1000 p o wer (dbm) frequenc y offset (khz) 3.6 v , +25c 1.8 v , +85c 3.6 v , ?40c 1.8 v , ?40c 3.6 v , +85c 1.8 v , +25c 08291-217 30 20 10 0 ?10 ?20 ?30 0 0.25 0.75 1.25 2.00 transmit frequency deviation (khz) transmit symbol (bits) 0.50 1.00 1.50 1.75 08291-218
data sheet adf7023 rev. c | page 23 of 112 figure 23 . transmit eye at 868 mhz, gfsk, data rate = 300 kbps, frequency deviation = 75 khz figure 24 . ook transmit spectrum, max hold for 100 sweeps, single - ended pa, 868.95 mhz, data rate = 16.4 kbps (32.8 kcps, manchester encoded), pa_ramp = 1 figure 25 . modulation error rat io (mer) vs. data rate, synthesizer loop bandwidth, and rf frequency at modulation index = 1 figure 26 . modulation error ratio (mer) vs . rf frequency, temperature , and v dd at modulation index = 1 and data rate = 10 kbps (minimum recommended v dd = 2.2 v, 1.8 v operation shown for robustness) figure 27 . modula tion error ratio (mer) vs. data rate, synthesizer loop bandwidth , and rf frequency at modulation index = 0.5 figure 28 . modulation error ratio (mer) vs . rf frequency, temperature , and v dd at modulation index = 0.5 and data rate = 10 kbps 100 50 0 ?25 ?50 ?75 ?100 0 0.25 0.75 1.25 2.00 transmit frequency deviation (khz) transmit symbol (bits) 75 25 0.50 1.00 1.50 1.75 08291-219 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 output power (dbm) frequenc y offset (mhz) 08291-221 22 23 24 25 26 27 28 29 30 31 32 33 34 10. 0 49.5 49.6 129.5 129.6 179.1 179.2 239.9 240.0 300.0 modulation error ratio (db) data rate (kbps) rf frequency = 868mhz rf frequency = 928mhz 381khz synth bandwidth 304khz synth bandwidth 223khz synth bandwidth 174khz synth bandwidth 130khz synth bandwidth 08291-220 23 24 25 26 27 28 29 30 31 32 860 870 880 890 900 910 920 930 940 modul a tion error r a tio (db) rf transmit frequenc y (mhz) +25c, 3.6v +85c, 3.6v ?40c, 3.6v +25c, 1.8v +85c, 1.8v ?40c, 1.8v 08291-222 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 10.0 49.5 49.6 129.5 129.6 179.1 179.2 239.9 240.0 300.0 modul a tion error r a tio (db) dat a r a te (kbps) 381khz synth bandwidth 304khz synth bandwidth 223khz synth bandwidth 174khz synth bandwidth 130khz synth bandwidth rf frequency = 868mhz rf frequency = 928mhz 08291-223 23 24 25 26 27 28 29 30 31 32 860 870 880 890 900 910 920 930 940 modul a tion error r a tio (db) rf transmit frequenc y (mhz) +25c, 3.6v +85c, 3.6v ?40c, 3.6v +25c, 1.8v +85c, 1.8v ?40c, 1.8v 08291-224
adf7023 data sheet rev. c | page 24 of 112 figure 29 . lna/mixer 1 db compression point, v dd = 3.0 v, temperature = 25 c, rf frequency = 915 mhz, lna gain = low, mixer gain = low figure 30 . lna/mixer 1 db compression point, v dd = 3.0 v, temperature = 25 c, rf frequency = 915 mhz, lna gain = high, mixer gain = high figure 31 . lna/mixer i i p3, v dd = 3.0 v, temperature = 25 c, rf frequency = 915 mhz, l na gain = low, mixer gain = low, source 1 frequency = (915 + 0.4) mhz, source 2 frequency = (915+ 0.7) mhz figure 32 . lna/mixer i i p3, v dd = 3.0 v, temperature = 25 c, rf frequency = 915 mhz, lna gain = high, mixer gain = high, source 1 freque ncy = (915 + 0.4) mhz, source 2 frequency = (915+ 0.7) mhz figure 33 . if filter profile vs. if bandwidth, v dd = 3.0 v, temperature = 25 c figure 34 . if filter profile vs. v dd and temperature, 100 khz if filter bandwidth (minimum recommended v dd = 2.2 v, 1.8 v operation shown for robustness) ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 ?40 ?35 ?30 ?25 ?20 ?15 mixer output power (dbm) ln a input power (dbm) output power (fundamen t al) output power idea l p1db p1db = ?21dbm 08291-225 output power (fundamen t al) output power idea l p1db ?10 ?5 0 5 10 15 20 ?40 ?35 ?30 ?25 ?20 ?15 mixer output power (dbm) ln a input power (dbm) p1db = ?21.9dbm 08291-226 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 mixer output power (dbm) ln a input power (dbm) fundamen tal t one im3 t one fundamen tal 1/1 slope fit im3 3/1 slope fit iip3 = ? 1 1.5dbm 08291-227 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 mixer output power (dbm) ln a input power (dbm) iip3 = ?12.2dbm fundamen tal t one im3 t one fundamen tal 1/1 slope fit im3 3/1 slope fit 08291-228 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 a ttenu a tion (db) frequenc y offset (mhz) 100khz 150khz 200khz 300khz 08291-229 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 a ttenu a tion (db) frequenc y offset (mhz) 3.6 v , +85c 1.8 v , ?40c 2.4 v , ?40c 3.0 v , ?40c 3.6 v , ?40c 1.8 v , +25c 2.4 v , +25c 3.0 v , +25c 3.6 v , +25c 1.8 v , +85c 2.4 v , +85c 3.0 v , +85c 08291-230
data sheet adf7023 rev. c | page 25 of 112 figure 35 . receiver wideband blocking at 433 mhz, data r ate = 38.4 kbps figure 36 . receiver wideband blocking at 433 mhz, data r ate = 100 kbps figure 37 . receiver wideband blocking at 433 mhz, data r ate = 300 kbps figure 38 . receiver wideband blocking to 60 mhz, at 868 mhz, data r ate = 38.4 kbp s, carrier wave interferer figure 39 . receiver wideband blocking at 868 mhz, data r ate = 100 kbps figure 40 . receiver wideband blocking at 868 mhz, data r ate = 300 kbps ?10 0 10 20 30 40 50 60 70 80 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 14 16 18 20 blocking (db) interferer offset from receiver lo frequenc y (mhz) modul ated interferer carrier wave interferer 08291-231 ?20 ?10 0 10 20 30 40 50 60 70 80 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 14 16 18 20 blocking (db) interferer offset from receiver lo frequenc y (mhz) modul ated interferer carrier wave interferer 08291-232 ?20 ?10 0 10 20 30 40 50 60 70 blocking (db) ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 14 16 18 20 interferer offset from receiver lo frequenc y (mhz) modul ated interferer carrier wave interferer 08291-233 ?10 0 10 20 30 40 50 60 70 80 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 blocking (db) blocker frequenc y offset (mhz) 08291-234 ?10 0 10 20 30 40 50 60 70 80 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 8 9 10 11 blocking (db) blocker frequenc y offset (mhz) modul ated interferer carrier wave interferer 08291-235 interferer offset from receiver lo frequenc y (mhz) ?10 ?20 0 10 20 30 40 50 60 70 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 8 9 10 11 blocking (db) modul ated interferer carrier wave interferer 08291-236
adf7023 data sheet rev. c | page 26 of 112 figure 41 . receiver wideband blocking at 915 mhz, data r ate = 38.4 kbps figure 42 . receiver wideband blocking at 915 mhz, data r ate = 100 kbps figure 43 . receiver wideband blocking at 915 mhz, data r ate = 300 kbps figure 44 . receiver wideband blocking vs . v dd and temperature, 915 mhz, data r ate = 300 kbps figure 45 . receiver wideband blocking at 868 mhz, data rate = 38.4 kbps, m easured as per etsi en 300 220 figure 46 . receiver close -i n blocking at 915 mhz, data r ate = 50 kbps, if filter bandwidth = 100 khz, image calibrated ?10 0 10 20 30 40 50 60 70 80 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 8 9 10 11 blocking (db) modul ated interferer carrier wave interferer interferer offset from receiver lo frequenc y (mhz) 08291-237 ?20 ?10 0 10 20 30 40 50 60 70 80 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 8 9 10 bl o cking (db) blocker frequenc y offset (mhz) modul ated interferer carrier wave interferer 08291-238 interferer offset from receiver lo frequenc y (mhz) ?10 ?20 0 10 20 30 40 50 60 70 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 8 9 10 11 blocking (db) modul ated interferer carrier wave interferer 08291-239 ?20 ?10 0 10 20 30 40 50 60 70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 blocking (db) interferer frequenc y offset (mhz) +25c 1.8v +25c 3.0v +25c 3.6v +85c 1.8v +85c 3.0v +85c 3.6v ?40c 1.8v ?40c 3.0v ?40c 3.6v 08291-240 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 interferer power (dbm) interferer offset from receiver lo frequenc y (mhz) gfsk, 100khz if bandwidth gfsk, 200khz if bandwidth 2fsk, 100khz if bandwidth 08291-241 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 2.0 blocking (db) interferer offset from receiver lo frequenc y (mhz) cw interferer modulated interferer 08291-242
data sheet adf7023 rev. c | page 27 of 112 figure 47 . receiver close -i n blocking at 915 mhz, data r ate = 100 kbps, if filter bandwidth = 100 khz, image calibrated figure 48 . receiver close -i n blocking at 915 mhz, data r ate = 150 kbps, if filter bandwidth = 150 khz, image calibrated figure 49 . receiver close -i n blocking at 915 mhz, data r ate = 200 kbps, if filter bandwidth = 200 khz, image calibrated figure 50 . receiver close -i n blo cking at 915 mhz, data r ate = 300 kbps, if filter bandwidth = 300 khz, image calibrated figure 51 . image attenuation with calibrated and uncalibrated image s, 915 mhz, if filter bandwidth = 1 00 khz, v dd = 3.0 v, temperature = 25 c figure 52 . image attenuation with calibrated and uncalibrated image s, 433 mhz, if filter bandwidth =100 khz, v dd = 3.0 v, temperature = 25c ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 40 45 50 55 60 ?2.0 ?1. 6 ?1.2 ?0.8 ?0.4 0 0. 4 0.8 1.2 1.6 2.0 blocking (db) interferer offset from receiver lo frequenc y (mhz) cw interferer modulated interferer 08291-243 ?2.0 ?1.6 ?1.2 0 0.4 0.8 1.2 1.6 2.0 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 40 45 50 55 60 blocking (db) interferer offset from receiver lo frequenc y (mhz) cw interferer modulated interferer 08291-244 ?0.8 ?0.4 ?2.0 ?1.6 ?1.2 0 0.4 0.8 1.2 1.6 2.0 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 40 45 50 55 60 blocking (db) interferer offset from receiver lo frequenc y (mhz) cw interferer modulated interferer 08291-245 ?0.8 ?0.4 ?2.0 ?1.6 ?1.2 0 0.4 0.8 1.2 1.6 2.0 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 40 45 50 55 60 blocking (db) interferer offset from receiver lo frequenc y (mhz) cw interferer modulated interferer 08291-246 ?0.8 ?0.4 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 a ttenu a tion (db) interferer offset from receiver lo frequenc y (mhz) calibrated uncalibrated 08291-247 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 a ttenu a tion (db) interferer offset from receiver lo frequenc y (mhz) calibrated uncalibrated 08291-248
adf7023 data sheet rev. c | page 28 of 112 figure 53 . if filter profile with calibrated image vs . if filter bandwidth, 921 mhz, v dd = 3.0 v, temperature = 25 c figure 54 . receiver sensitivity (bit error rate at 1e ? 3) vs. v dd , temp erature, and rf frequency, data r ate = 300 kbps, gfsk, frequency deviation = 75 khz, if bandwidth = 300 khz figure 55 . bit error rate sensitivity (at ber = 1e ? 3) and packet error rate sensitivity (at per = 1%) vs . data r ate, gfsk, v dd = 3.0 v, temperature = 25 c figure 56 . packet error ra te vs. rf input power and data r ate, fsk/gfsk, 928 mhz, preamble length = 64 b its, v dd = 3.0 v, temperature = 25 c figure 57 . receiver sensitivity (packet error rate at 1%) vs. v dd , temperature , and rf frequency, data r ate = 300 kbps, gfsk, frequency deviation = 75 khz, if bandwidth = 300 khz figure 58 . receiver per using reed solomon (rs) coding; rf frequency = 915 mhz, gfsk, data rate = 300 kbps, frequency devia tion =75 khz, packet lengt h = 28 bytes (u ncoded) ; reed solomon configuration: n = 38, k = 28, t =5 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 a ttenu a tion (db) offset from lo frequenc y (mhz) 100khz bw 150khz bw 200khz bw 300khz bw 08291-249 ?104 ?103 ?102 ?101 ?100 ?99 ?98 1.8 3.0 3.6 sensitivity (dbm) v dd (v) 915mhz, ?40c 915mhz, +25c 915mhz, +85c 868mhz, ?40c 868mhz, +25c 868mhz, +85c 08291-250 ?120 ?1 15 ?1 10 ?105 ?100 ?95 0 50 100 150 200 250 300 sensitivity (dbm) dat a r a te (kbps) bit error rate (1e-3) packet error rate (1%) 08291-251 0 10 20 30 40 50 60 70 80 90 100 p acket error r a te (%) applied receiver power (dbm) 1kbps 10kbps 38.4kbps 50kbps 100kbps 200kbps 300kbps ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 0 ?10 ?40 ?30 ?20 08291-252 ?100.0 ?99.5 ?99.0 ?98.5 ?98.0 ?97.5 ?97.0 ?96.5 ?96.0 1.8 3. 6 sensitivity (dbm) v dd (v) ?40c +25c +85c 08291-254 0 1 2 3 4 5 6 7 8 9 10 ?104 ?103 ?102 ?101 ?100 ?99 ?98 ?97 ?96 ?95 ?94 per (%) receiver input power (dbm) rs coded data, sync_error_tol = 0, preamble_match = 0xa rs coded data, sync_error_tol = 1, preamble_match = 0x0a uncoded data, sync_error_tol = 0 2db 3.4db 08291-253
data sheet adf7023 rev. c | page 29 of 112 figure 59 . ook packet error rate vs. rf input power, data rate = 19.2 kbps (chip r ate = 38.4 kcps, manchester e ncoded), if bandwidth = 100 khz, v dd = 3.6 v, temperature = 25 c, rf frequency = 902 mhz, preamble length = 100 b its figure 60 . ook packet error rate vs. rf input power, data rate = 2.4 kbps (chip r ate = 4.8 kcps, manchester e ncoded), if bandwidth = 100 khz, v dd = 3.6 v, temperature = 25 c, rf frequency = 902 mhz, preamble length = 100 b its figure 61 . ook packet error rate vs. rf input power, v dd , and temperature, data rate = 19.2 kbps ( chip r ate = 38.4 kcps, manchester e ncoded), if bandwidth = 100 khz, v dd = 3.6 v, temperature = 25 c, rf frequency = 902 mhz, preamble length = 100 b its (minimum recommended v dd = 2.2 v, 1.8 v operation shown for robustness) figure 62 . ook packet error rate vs. rf input power and ook modulation depth, data rate = 19.2 kbps (chip r ate = 38.4 kcps, manchester e ncoded), if bandwidth = 100 khz, v dd = 3.6 v, temperature = 25 c, rf frequency = 902 mhz, preamble length = 100 b its figure 63 . afc on : receiver sensitivity (at per = 1%) vs. rf frequency error, gfsk, 915 mhz, afc enabled (ki = 7, kp = 3), afc mode = lock after preamble, if bandwidth = 100 khz ( at 100 kbps), 150 khz ( at 150 kbps), 200 khz ( at 200 kbps) , and 300 khz ( at 300 kbps), preamble length = 64 b its figure 64 . afc off : packet error rate vs. rf frequency error and d ata rate error, data rate = 300 kbps, frequency deviation = 75 khz, gfsk, agc_ lock _ mode = lock a fter p reamble 100 0 10 20 30 40 50 60 70 80 90 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 packet error rate (%) applied power (dbm) 08291-255 100 0 10 20 30 40 50 60 70 80 90 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 packet error rate (%) applied power (dbm) 08291-256 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 ?106 ?105 ?104 ?103 ?102 ?101 packet error rate (%) applied power (dbm) t a = ?40c, v dd = 1.8v t a = ?40c, v dd = 3.6v t a = +25c, v dd = 1.8v t a = +25c, v dd = 3.6v t a = +85c, v dd = 1.8v t a = +85c, v dd = 3.6v 08291-257 100 0 10 20 30 40 50 60 70 80 90 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 packet error rate (%) applied power (dbm) ook modulation depth = 60db ook modulation depth = 40db ook modulation depth = 30db ook modulation depth = 20db 08291-258 0 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?150 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 sensitivity (dbm) rf frequency error (khz) 100kbps 150kbps 200kbps 300kbps 08291-259 2.00 ?2.00 ?1.75 ?1.50 ?1.25 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 data rate error (%) ?40 ?30 ?20 ?10 0 10 20 30 ?35 ?25 ?15 ?5 5 15 25 35 40 rf frequency error (khz) >1% <1% 08291-260
adf7023 data sheet rev. c | page 30 of 112 figure 65 . afc on: packet error rate vs. rf frequency error and data rate erro r , data rate = 300 kbps, frequency deviation = 75 khz, gfsk, agc_ lock _ mode = lock a fter p reamble figure 66 . rssi (via cmd_get_rssi) vs. rf input power, 868 mhz, gfsk, data rate = 38.4 kbps, frequency deviation = 20 khz, if bandwidth = 100 khz, 100 rssi measurements at e ach input power level figure 67 . rssi (via a utomatic e nd of p acket rssi m easurement) vs . rf input power, 868 mhz, gfsk, data rate = 300 kbps, frequency deviation = 75 khz, if bandwidth = 300 khz, agc_clock_divide = 15, 100 rssi measurements at e ach input power level figure 68 . mean rssi er r or (via automatic end of packet rssi measurement) vs. rf input power vs. data rate; rf frequency = 868 mhz, gfsk, 100 rssi measurements at each input power level figure 69 . rssi w ith and without cosine polynomial correction (via automatic end of packet rssi m easurem ent), 100 rssi measurements at e ach input power level figure 70 . ook rssi and ook rssi error vs . rf input power. 915 mhz, data rate = 19.2 kbps (38.4 kcps), 200 rssi measurements per input power level 2.00 ?2.00 ?1.75 ?1.50 ?1.25 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 data rate error (%) ?140?120?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 120 140 rf frequency error (khz) >1% <1% 08291-261 ?20 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 rssi (dbm) rssi error (db) ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 input power (dbm) ideal rssi mean rssi mean rssi error max positive rssi error max negative rssi error 08291-262 ?20 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 rssi (dbm) rssi error (db) ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 input power (dbm) ideal rssi mean rssi mean rssi error max positive rssi error max negative rssi error 08291-263 6 ?6 ?4 ?2 0 2 4 rssi error (db) ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 input power (dbm) 300kbps 200kbps 150kbps 100kbps 50kbps 38.4kbps 9.6kbps 08291-264 ?20 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 rssi (dbm) rssi error (db) ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 input power (dbm) ideal rssi mean rssi mean rssi (with polynomial correction) mean rssi error mean rssi error (with polynomial correction) 08291-265 ?20 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 rssi (dbm) rssi error (db) ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 input power (dbm) ideal rssi mean rssi mean rssi error max positive rssi error max negative rssi error 08291-266
data sheet adf7023 rev. c | page 31 of 112 figure 71 . ook rssi vs . rf input power, v dd , and temperature , rf frequency = 915 mhz, data rate = 19.2 kbps (38.4 kcps manchester e ncoded) figure 72 . typical accuracy range of temperature sensor vs. a pplied t emperature , calibration performed at 25c figure 73 . receiver eye diagram measured using the test dac. , rf frequency = 915 mhz, rf input p ower = ? 80 dbm, data rate = 100 kbps, frequency deviation = 50 khz figure 74 . recei ver eye diagram measured using the test dac, rf frequency = 915 mhz, rf input power = ? 105 dbm, data rate = 100 kbps, frequency deviation = 50 khz ?20 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 rssi (dbm) ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 input power (dbm) ideal rssi 1.8v @ 25c 3.6v @ 25c 1.8v @ 85c 3.6v @ 85c 08291-267 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 tempera ture calcul a ted from sensor (c) applied temper a ture (c) error mean accuracy 08291-170 ?1 1 receiver symbol level 0 1 2 3 4 5 6 7 8 9 sample number 08291-269 ?1 1 receiver symbol level 0 1 2 3 4 5 6 7 8 9 sample number 08291-270
adf7023 data sheet rev. c | page 32 of 112 terminology adc analog to d igital c onverter agc automatic gain c ontrol afc automatic frequency co ntrol battmon battery m onitor bbram battery back up r andom a ccess m emory cbc cipher block chaining crc cyclic redundancy c heck dr data r ate ecb electronic code book ecc error checking code 2 fsk two - level frequency s hift k eying gfsk two - level gaussian f requency s hift k eying gmsk gaussian minimum shift keying lo local o scillator mac media a ccess c ontrol mcr modem c onfiguration r andom access memory mer modulation e rror r ate msk minimum shift keying nop no o peration ook on-o ff k eying pa power a mplifier pfd phase f requency d etector phy physical l ayer rco rc o scillator risc reduced i nstruction set c omputer rssi receive s ignal strength i ndicator rx receive sar successive approximation register swm smart w ake m ode tx transmit vco voltage c ontrolled o scillator wuc wa ke - up c ontroller xosc crystal o scillator
data sheet adf7023 rev. c | page 33 of 112 radio control the adf7023 has five radio states designated phy_sleep, phy_off, phy_on, phy_rx , and phy_tx. the host processor ca n transition the adf7023 between states by issuing single byte commands over the spi interface. the various commands and states are illustrate d in figure 75 . the communications processor handles the sequencing of various radio circuits and critical timing functions , thereby simplifying radio operation and eas ing the burden on the host processor. radio states phy_sleep in this state, the device is in a low power sleep mode. to enter the state , issue the cmd_phy_sleep command, either f rom the phy_off or phy_on state . to wake the radio from the state , set the cs pin low, or use the wake - up controller (32.768 khz rc or 32.768 khz crystal) t o wake the radio from this state. the wake - up timer should be set up before entering the phy_sleep state. if retention of bbram contents is no t required , deep sleep mode 2 can be used to further reduce the phy_sleep state current consumption. deep sleep mode 2 is entered by issuing the cmd_hw_reset command. the options for the phy_sleep state are detailed in table 10 . when in phy_sleep, the irq_gp3 interrupt pin is held at logic low while the other gp x pins are in a high impedance state. phy_off in the phy_off state, t he 26 mhz crystal, the digital regula tor , and the synthesizer regulator are powered up. all memories are fully accessible. the bbram registers must be valid before exiting this state. phy_on in the phy_on state, a long with the crystal, the digital regulator and the synthesizer regulator, vco , and rf regulators are powered up. a baseband filter calibration is performed when this state is entered from the phy_off state if the bb _ cal bit in the mode _ control register (address 0x11a) is set. the device is ready to ope rate , and the phy_tx and phy_rx states can be entered. phy_tx in the phy_tx state, t he synthesizer is enabled and calibrated. the power amplifier is enabled , and the device transmits at the ch annel frequency defined by the channel _ freq [23:0] setting ( address 0x109 to address 0x10b). th e state is entered by issuing the cmd_phy_tx command. the device automatically transmits the transmit packet stored in the packet ram. after transmission of the packet, the pa is disabled and the device automatically returns to the phy_on state and can, op tionally , generate an interrupt. in sport mode , the device transmit s the data present on the gp2 pin as described in the sport section. the host processor must issue the cmd_phy_on command to exit the phy_tx state when in sport mode. phy_rx in the phy_rx state, t he synthesizer is enabled and calibrated. the adc, rssi, if filter, mixer , and lna are enabled. the radio is in receive mode on the channel frequency defined by the channel_freq[23:0] setting (address 0x109 to address 0x10b). after reception of a valid packet, the device returns to the phy_on state and can , opt ionally , generate an interrupt. in sport mode , the device remains in the phy_rx state until the cmd_phy_on command is issued. current consumption the typical current consumption in each state is detailed in table 10. table 10 . current consumption in adf7023 r adio s tates state current (t ypical) conditions phy_sleep (d eep sleep m ode 2) 0.18 a wake - up timer off, bbram contents not retained, e ntered by issuing cmd_hw_reset phy_sleep (d eep sleep m ode 1) 0.3 3 a wake - up timer off, bbram contents retained phy_sleep (rco m ode ) 0. 75 a wake - up timer on using a 32 khz rc oscillator, bbram contents retained phy_sleep (xto m ode ) 1.2 8 a wake - up timer on using a 32 khz xtal oscillator, bbram contents retained phy_off 1.0 ma phy_on 1.0 ma phy_tx 24.1 ma 10 dbm, single - ended pa, 868 mhz phy_rx 12.8 ma
adf7023 data sheet rev. c | page 34 of 112 figure 75 . radio state diagram configure program ram config aes ir calibration reed-solomon if filter cal configure measure rssi rx_to_tx_auto_turnaround 1 tx_to_rx_auto_turnaround 1 cmd_phy_tx cmd_phy_tx cmd_phy_rx cmd_phy_sleep cmd_phy_on cmd_phy_on cmd_phy_on cmd_phy_off cmd_phy_rx cold start (battery applied) cmd_config_dev cmd_ram_load_init cmd_ram_load_done cmd_aes cmd_ir_cal cmd_aes 4 cs low wuc timeout cmd_phy_sleep cmd_hw_reset (from any state) phy_on phy_tx phy_rx cmd_phy_rx cmd_phy_tx tx_eof 3 rx_eof 3 phy_off phy_sleep cmd_rs 5 cmd_config_dev cmd_bb_cal cmd_get_rssi program ram 2 08291-121 1 transmit and receive automatic turnaround must be enabled by bits rx_to_tx_auto_turnaround and tx_to_rx_auto_turnaround (0x11a: mode_control). 2 aes encryption/decryption, image rejection calibration, and reed solomon coding are available only if the necessary firmware module has been downloaded to the program ram. 3 the end of frame (eof) automatic transitions are disabled in sport mode. 4 cmd_aes refers to the three available aes commands: cmd_aes_encrypt, cmd_aes_decrypt, and cmd_aes_decrypt_init. 5 cmd_rs refers to the three available reed solomon commands: cmd_rs_encode_init, cmd_rs_encode, and cmd_rs_decode. key transition initiated by host processor automatic transition by communications processor communications processor function downloadable firmware module stored on program ram radio state 4
data sheet adf7023 rev. c | page 35 of 112 initialization initialization after application of power when power is applied to the adf7023 ( t hrough the vddbat1/ vddbat2 pins ), it registers a power - on reset event (por) and transitions to the phy_off state. the bbram memory is unknown, the packet ram memory is cleared to 0x00 , and the mcr memory is reset to its default values. the host processor should use the following procedure to complete the initialization sequence : 1. bring the cs pin of the s pi low and wait until the miso output goes high. 2. poll status word and wait for the cmd_ready bit to go high. 3. configure the part by writing to all 64 of the bbram registers. 4. issue the cmd_config_dev command so that the radio settings are updated using the bbram values. the adf7023 is now configured in the phy_off state. initialization after issuing the cmd_hw_reset command the cmd_hw_reset command performs a full power - down of all hardware , and the device enters the phy_sleep state . to complete the hardwar e reset , the host processor should complete the following procedure : 1. wait for 1 ms . 2. bring the cs pin of the spi low and wait until the miso output goes high. the adf7023 registers a por and enters the phy_off state . 3. poll status word and wait for the cmd_ready bit to go high. 4. configure the part by writing to all 64 of the bbram registers. 5. issue the cmd_config_dev command so that the radio settings are updated using the bbram values. the adf7023 is now configured in th e phy_off state . initialization on transitioning from phy_ sleep (a fter cs is brought low ) the host processor can bring cs low at an y time to wake the adf7023 from the phy_sleep state. this event is not registered as a po r event because the bbram contents are valid. the following is the procedure that the host processor is required to follow: 1. bring the cs line of the spi low and wait until the miso output goes high. the adf7023 enters the phy_off state . 2. poll status word and w ait for the cmd _ ready bit to go high. 3. issue the cmd_config_dev command so that the radio settings are updated using the bbram values. the adf7023 is now configured and ready to transition to the phy_on state . initialization after a wuc t imeout the adf7023 can autonomously wake from the p hy_sleep state using the wake - up controller. if the adf7023 wakes after a wuc timeout in smart wake mode (swm) , it follows the swm routine based on the smart wake mode configuration in bbram (see the low power modes s ection). if the adf7023 wakes after a wuc timeout with swm disabled and the firmware timer disabled, it wakes in the phy_off state, an d the following is t he procedure that the host processor is required to follow: 1. poll status word and wait for the cmd_ready bit to go high. 2. issue the cmd_config_dev command so that the radio settings are updated using the bbram values. the adf7023 is now configured in the phy_off state. commands the commands that are supported by the radio controller are detailed in this section. they initiate transitions between radio states or perform tasks as indicated in figure 75 . cmd_phy_off (0xb0) this command transitions the adf7023 to the phy_off state . it can be issued in the phy_on state . it powers down the rf and vco regulators. cmd_ phy_on (0xb1) this comman d transitions the adf7023 to the phy_on state. if the command is issued in the phy_off state, it powers up the rf and vco regulators and performs an if filter calibration if the bb_cal bit is set in the mode_control register (address 0x11a). if the comma nd is issued from the phy_tx state, the host processor performs the following procedure : 1. ramp down the pa . 2. set the external pa signal low (if enabled) . 3. turn off the digital transmit clocks . 4. power down the synthesizer . 5. set fw_ state = phy_on . if the command is issued from the phy_rx state, the communications processor performs the following procedure : 1. copy the measured rssi to the rssi _ readback register. 2. set the external lna signal low (if enabled) . 3. turn off the digital receiver clocks . 4. power down the synthesizer and the receiver circuitry (adc, rssi, if filter, mixer , and lna) . 5. set fw_ state = phy_on .
adf7023 data sheet rev. c | page 36 of 112 cmd_phy_sleep (0xba) this command transitions the adf7023 to the very low power phy_sleep state in which the wuc is operational (if enabled) , and the bbra m contents are retained. it can be issued f rom the phy_off or phy_on state . cmd_phy_rx (0xb2) this command can be issued in the phy_on, phy_rx, or phy_tx state . if the command is issued in the phy_on state, the communications processor performs the followi ng pr oce dure : 1. power up the synthesizer. 2. power up the receiver circuitry (adc, rssi, if filter, mixer , and lna). 3. set the rf channel based on the channel_freq[ 23 :0] setting in bbram . 4. set the synthesizer bandwidth. 5. do vco calibration. 6. delay for synthesizer s ettling. 7. enable the digital receiver blocks . 8. set the external lna enable signal high (if enabled). 9. set fw_ state = phy_rx. if the command is issued in the phy_rx state, the communications processor performs the following pro c edure : 1. set the external lna sign al low (if enabled). 2. unlock the afc and agc. 3. turn off the receive b locks. 4. set the rf channel based on the channel_freq[ 23 :0] setting in bbram. 5. set the synthesizer bandwidth. 6. do vco calibration. 7. delay for synthesizer settling. 8. enable the digital receiver b locks . 9. set the external lna enable signal high (if enabled). 10. set fw_ state = phy_rx. if the command is issued in the phy_tx state, the communications processor performs the following procedure : 1. ramp down the pa. 2. set the external pa signal low (if enabled). 3. turn off the digital transmit blocks . 4. power up the receiver circuitry (adc, rssi, if filter, mixer , and lna). 5. set the rf channel based on the channel_freq[ 23 :0] setting in bbram. 6. set the synthesizer bandwidth. 7. do vco calibration. 8. delay for synthesizer set tling. 9. enable the digital receiver blocks . 10. set the external lna enable signal high (if enabled). 11. set fw_ state = phy_rx cmd_phy_tx (0xb5) this command can be issued in the phy_on, phy_tx, or phy_rx state . if the command is issued in the phy_on state, the co mmunications processor performs the following procedure : 1. power up the synthesizer. 2. set the rf channel based on the channel_freq[ 23 :0] setting in bbram. 3. set the synthesizer bandwidth. 4. do vco calibration. 5. delay for synthesizer settling. 6. enable the digital t ransmit blocks . 7. set the external pa enable signal high (if enabled). 8. ramp up the pa. 9. set fw_ state = phy_tx. 10. t ransmit data. i f the command is issued in the phy_tx state, the communi - cations processor performs the fol lowing procedure : 1. ramp down the pa. 2. set the external pa enable signal low (if enabled). 3. turn of f the digital transmit blocks . 4. set the rf channel based on the channel_freq[ 23 :0] setting in bbram. 5. set the synthesizer bandwidth. 6. do vco calibration. 7. delay for synthesizer settling. 8. enable the digita l transmit blocks . 9. set the external pa enable signal high (if enabled). 10. ramp up the pa. 11. set fw_ state = phy_tx. 12. transmit data. if the command is issued in the phy_rx state, the communi - cations processor performs the following procedure : 1. set the external lna signal low (if enabled). 2. unlock the afc and agc. 3. turn off the receive blocks . 4. power down the receiver circuitry (adc, rssi, if filter, mixer , and lna). 5. set the rf channel based on the channel_freq[ 23 :0] setting in bbram. 6. set the synthesizer bandwidth. 7. de lay for synthesizer settling. 8. enable the digital transmit blocks . 9. set the external pa enable signal high (if enabled). 10. ramp up the pa. 11. set fw_ state = phy_tx. 12. transmit data.
data sheet adf7023 rev. c | page 37 of 112 cmd_config_dev (0xbb) this command interprets the bbram contents and configures each of the radio parameters based on these contents. it can be issued from the phy_off or phy_on state. the only radio parameter that isnt configured on this command is the channel_freq[ 23 :0] setting, which instead is configured as part of a cmd_phy_tx o r cmd_phy_rx command. the user should write to the entire 64 bytes of the bbram and then issue the cmd_config_dev command , which can be issued in the phy_off or phy_on state. cmd_get_rssi (0xbc) this command turns on the receiver , performs an rssi measur ement on the current channel , and returns the adf7023 to the phy_on state . the command can be issued from the phy_on state. the rssi result is saved to the rssi _ readback register ( address 0x312). this command can be issued from the phy_on state only . cmd_bb_cal (0xbe) this command performs an if filter calibration. it can be issued only in the phy_on state. in many cases , it may not be necessary to use this command because an if filter calibration is automatically performed on the phy_off to phy_on tra nsition if bb _ cal = 1 in the mode _ control register ( address 0x11a). cmd_hw_reset (0xc8) th e command performs a full power - down of all hardware , and the device enters the phy_sleep state . this command can be issued in any state and is independent of the sta te of the communications processor. the procedure for initializ ation of the device after a cmd_hw_reset command is described in detail in the initialization section. c md_ram_load_init (0xbf) this command prepares the communications processor for a subsequent download of a software module to program ram. this command should be issued only prior to the program ram be ing written to by the host processor. cmd_ra m_load_done (0xc7) this command is required only after download of a software module to program ram. it indicates to the communications processor that a software module is loaded to program ram. t he cmd_ram_load_done command can be issued only in the phy_off state . the command reset s the communications processor and the packet ram. cmd_ir_cal (0xbd) this command performs a fully automatic image rejection calibration on the adf7023 receiver. this command requires that the ir calibration firmware module has been loaded to the adf7023 program ram. the firmware module is available from analog devices. for more information , see the downloadable firmware modules s ection . cmd_aes_encr ypt (0xd0), cmd_aes_decrypt (0xd2 ), and cmd_aes_decrypt_init (0xd 1) these commands allow aes, 128 - bit block encryption and decryption of transmit and receive data using key sizes of 128 bits, 192 bits, or 256 bits. the aes commands require that the aes firmware module has been loaded to the adf7023 program ram. the aes firmware module is available from analog devices. see the downloadable firmware modules section for details on the aes encryption and decryption module . cmd_rs_encode_init (0xd1), cmd_rs_encode (0xd0 ), and cmd_rs_decode (0xd2) these commands perform reed solomon encoding and decoding of transmit and receive data, thereby allowing d etection and correct ion of errors in the received packet. these commands require that the reed solomon firmware module has been loaded to the adf7023 program ram. the reed solomon firmware module is available from analog devices. see the downloadable firmware modules s e ction for details on this module . automatic state tran sitions on certain events , the communications processor can automatically transit ion the adf7023 between states. these automatic transitions are illustrated as dashed lines in figure 75 and are explained in this section .
adf7023 data sheet rev. c | page 38 of 11 2 tx_eof th e communications processor automatically transition s the device from the phy_tx state to the phy_on state at the end of a packet transmission. on the transition, the communications processor performs the following actions: 1. ramps down the pa. 2. sets the external pa signal low . 3. disables the digital transmitter blocks . 4. powers down the synthesizer. 5. sets fw_ state = phy_on. rx_eof the communications processor automatically transitions the device from the phy_rx state to the phy_on state at the end of a packet reception. on the tran sition, the communications processor performs the following actions: 1. copies the measured rssi to the rssi _ readback register (address 0x312) . 2. sets the external lna signal low. 3. disables the digital receiver blocks . 4. powers down the synthesizer and the receiver circuitry (adc, rssi, if filter, mixer , and lna). 5. sets fw_ state = phy_on. rx_to_tx_auto_turnaround if the rx_to_tx_auto_turnaround bit in the mode _ control register ( address 0x11a) is enabled , the device automatically transition s to the phy_tx state at the end of a valid packet reception , on the same rf channel frequency. on the transition, the communications processor performs the following actions: 1. sets the external lna signal low. 2. unlocks the agc and afc (if enabled). 3. disables the digital receiv er blocks . 4. powers down the receiver circuitry (adc, rssi, if filter, mixer , and lna). 5. sets rf channel frequency (same as the previous receive channel frequency ). 6. set s the synthesizer bandwidth. 7. do es vco calibration. 8. delay s for synthesizer settling. 9. enable s the digital transmitter blocks . 10. sets the external pa signal high (if enabled). 11. ramps up the pa. 12. sets fw_ state = phy_tx . 13. transmits data. in sport mode, the rx_to_tx_auto_turnaround transition is disabled. tx_to_rx_auto_turnaround if the tx_to_rx_auto_ turnaround bit in the mode _ control register ( address 0x11a) is enabled , the device automatically transition s to the phy_rx state at the end of a packet transmission, on the same rf channel frequency. on the transition, the communications processor performs the following actions: 1. ramps down the pa. 2. sets the external pa signal low. 3. disables the digital transmitter blocks . 4. powers up the receiver circuitry (adc, rssi, if filter, mixer , and lna). 5. set s the rf channel (same as the previous transmit channel frequency). 6. set s the synthesizer bandwidth. 7. do es vco calibration. 8. d elay s f or synthesizer settling. 9. turns on agc and afc (if enabled). 10. enables the digital receiver blocks . 11. sets the external lna signal high (if enabled). 12. sets fw_ state = phy_rx. in s port mode, the tx_to_rx_auto_turnaround transition is disabled. wuc t imeout the adf7023 can use the wuc to wake from sleep on a timeout of the hardware timer. the device wakes into the phy_off state. see the wuc mode section for further details. state transition and command timing the execution times for all radio state transitions are detailed in table 11 and table 12 . note that these times are typical and can vary , depending on the bbram c onfiguration. for normal transition times , set transition_clock_div (l ocation 0x13a) to 0x04. for fast transition times , set transition_clock_div to 0x01. it is recommended to enable fast transition times to reduce system power consumption. as stated in th e spi interface section, commands are executed on the last positive sclk edge of the command. for the values given in table 11 and table 12, there is an additional 200 ns between the last positive sclk edge and the rising edge of cs that is related to the spi rate used .
data sheet adf7023 rev. c | page 39 of 112 table 11 . adf7023 command execution times and state transition times t hat a re n ot r elated to phy_tx or phy_rx command/bit command initiated by present state next state normal transition time (s), typical fast transition time (s) typical condition cmd_hw_reset host any phy_sleep 1 1 cmd_phy_sleep host phy_off phy_sleep 22.3 22.3 cmd_phy_sleep host phy_on phy_sleep 24.1 24.1 cmd_phy_off host phy_on phy_off 24 11 from rising edge of cs to cmd_finished interrupt cmd_phy_on host phy_off phy_on 258/73 213/28 from rising edge of cs to cmd_finished interrupt ; if filter calibration enabled/disabled cmd_get_rssi host phy_on phy_on 631/450 523/353 rssi_wait_time ( address 0x138) = 0xa7/0x37 cmd_config_dev host phy_off phy_off 72 23 from rising edge of cs to cmd_finished interrupt cmd_config_dev host phy_on phy_on 75.5 24.5 from rising edge of cs to cmd_finished interrupt cmd_bb_cal host phy_on phy_on 221 204 from rising edge of cs to cmd_finished interrupt wake - up from phy_sleep, (wuc timeout) automatic phy_sleep phy_off 304 304 7 pf load capacitance, t a = 25c wake - up from phy_sleep, ( cs low) host phy_sleep phy_off 304 304 7 pf load capacitance, t a = 25c cold start application of power n/a phy_off 304 304 7 pf load capacitance, t a = 25c table 12. adf7023 state transition times r elated to phy_tx and phy_rx mode command/bit/ automatic transition present state next state normal transition time (s) 1 , 2 , typical fast transition time (s) 1 , 2 , typical condition packet cmd_phy_on phy_tx phy_on t eop + t paramp _down + t byte + 43 t eop + t paramp_down + t byte + 15 from rising edge of cs to cmd_finished interrupt packet cmd_phy_on phy_rx phy_on t byte + 48 t byte + 21 from rising edge of cs to cmd_finished interrupt, cmd_phy_on issued during search for preamble 50.5 23 from rising edge of cs to cmd_finished interrupt, cmd_phy_on issued during preamble qualification 50.5 23 from rising edge of cs to cmd_finished interrupt, cmd_phy_on issued during sync word qualification t eop + 62.5 t eop + 18 from rising edge of cs to cmd_finished interrupt, cmd_phy_on issued during rx data (after a sync word)
adf7023 data sheet rev. c | page 40 of 112 mode command/bit/ automatic transition present state next state normal transition time (s) 1 , 2 , typical fast transition time (s) 1 , 2 , typical condition packet cmd_phy_tx phy_on phy_tx 306 237 from rising edge of cs to cmd_finished interrupt ; pa ramp up starts 3.4 s after the interrupt ; first bit of user data is transmitted 1.5 t bit + 2.3 s following the interrupt packet cmd_phy_tx phy_rx phy_tx t byte + 324.5 t byte + 248 from rising edge of cs to cmd_finished interrupt, cmd_phy_ tx issued during search for preamble ; pa ramp up starts 3.4 s after the interrupt ; first bit of user data is transmitted 1.5 t bit + 2.3 s following the interr upt 322.5 245.5 from rising edge of cs to cmd_finished interrupt, cmd_phy_tx issued during preamble qualification ; pa ramp up starts 3.4 s after the interrupt ; first bit of user data is transmitted 1.5 t bit + 2.3 s following the interrupt 322.5 245.5 from rising edge of cs to cmd_finished interrupt, cmd_phy_tx issued during sync word qualification ; pa ramp up starts 3.4 s after the interrupt ; first bit of user data is transmitted 1.5 t bit + 2.3 s following the interrupt t eop + 281 t eop + 263 from rising edge of cs to cmd_finished i nterrupt, cmd_phy_tx issued during rx data (after a sync word) ; pa ramp up starts 3.4 s after the interrupt ; first bit of user data is transmitted 1.5 t bit + 2.3 s following the interrupt packet cmd_phy_tx phy_tx phy_tx t eop + t paramp_down + t byte + 310 t eop + t paramp _down + t byte + 236 from rising edge of cs to cmd_finished interrupt. cmd_phy_tx issued during packet transmission ; pa ramp up starts 3.4 s after the interrupt ; first bit of user data is transmitted 1.5 t bit + 2.3 s following the interrupt packet rx_to_tx_auto _turnaround phy_ rx phy_tx 322 234.2 from interrupt_crc_correct to cmd_finished interrupt ; pa ramp up starts 3.4 s after the interrupt ; first bit of user data is transmitted 1.5 t bit + 2.3 s following the interrupt packet cmd_phy_rx phy_on phy_rx 327 241 from rising edge of cs to cmd_finished interrupt packet cmd_phy_rx phy_tx phy_rx t eop + t paramp _down + t byte + 336 t eop + t paramp _down + t byte + 241 from rising edge of cs to cmd_finished interrupt ; cmd_phy_rx issued during packet transmission packet cmd_phy_rx phy_rx phy_rx t byte + 341.5 t byte + 249.5 from rising edge of cs to cmd_finished interrupt, cmd_phy_rx issued during search for preamble 339.5 249 from rising edge of cs to cmd_finished interrupt, cmd_phy_rx issued during preamble qualification 339.5 249 from rising edge of cs to cmd_finished interrupt, cmd_phy_rx issued during sync word qualification t eop + 354 t eop + 246 from rising edge of cs to cmd_finished interrupt, cmd_phy_rx issued during rx data (after a sync word)
data sheet adf7023 rev. c | page 41 of 112 mode command/bit/ automatic transition present state next state normal transition time (s) 1 , 2 , typical fast transition time (s) 1 , 2 , typical condition packet tx_to_rx_auto _turnaround phy_tx phy_rx t paramp _down + t byte + 322 t paramp _down + t byte + 232 from tx_eof interrupt to cmd_ finished interrupt packet tx_eof phy_tx phy_on t paramp _down + t byte + 25 t paramp _down + t byte + 5 from tx_eof interrupt to cmd_ finished interrupt packet rx_eof phy_rx phy_on 46 10 from interrupt_crc_correct to cmd_finished interrupt sport cmd_phy_on phy_tx phy_on t paramp _down + 51 t paramp _down + 22 from rising edge of cs to cmd_finished interrupt sport cmd_phy_on phy_rx phy_on t byte + 54 t byte + 28 from rising edge of cs to cmd_finished interrupt, cmd_phy_on issued during search for preamble 50.5 23 from rising edge of cs to cmd_finished interrupt, cmd_phy_on issued during preamble qualification 50.5 23 from rising edge of cs to cmd_finished interrupt, cmd_phy_on issued during sync word qualification 56 26 from rising edge of cs to cmd_finished interrupt, cmd_phy_on issued during rx data (after a sync word) sport cmd_phy_tx phy_on phy_tx 306 237 from rising edge of cs to cmd_finished interrupt ; pa ramp up starts 3.4 s after the interrupt sport cmd_phy_tx phy_rx phy_tx t byte + 325 t byte + 250 from rising edge of cs to cmd_finished interrupt, cmd_phy_tx issued during search for preamble ; pa ramp up starts 3.4 s after the interrupt 320 245 from rising edge of cs to cmd_finished interrupt, cmd_phy_tx issued during preamble qualification . the pa ramp up starts 3.4 s after the interrupt. 320 245 from rising edge of cs to cmd_finished interrupt, cmd_phy_tx issued during sync word qualification ; pa ramp up starts 3.4 s after the interrupt 326 249 from rising edge of cs to cmd_finished interrupt, cmd_phy_tx issued during rx data (after a sync word) . the pa ramp up starts 3.4 s after the interrupt. sport cmd_phy_tx phy_tx phy_tx t paramp _down + 315 t paramp _down + 243 from rising edge of cs to cmd_finished interrupt ; pa ramp up starts 3.4 s after the interrupt sport cmd_phy_rx phy_on phy_rx 327 241 from rising edge of cs to cmd_finished interrupt sport cmd_phy_rx phy_tx phy_rx t paramp _down + 345 t paramp _down + 250 from rising edge of cs to cmd_finished interrupt
adf7023 data sheet rev. c | page 42 of 112 mode command/bit/ automatic transition present state next state normal transition time (s) 1 , 2 , typical fast transition time (s) 1 , 2 , typical condition sport cmd_phy_rx phy_rx phy_rx t byte + 342 t byte + 249.5 from rising edge of cs to cmd_finished interrupt, cmd_phy_rx issued during search for preamble 339.5 249 from rising edge of cs to cmd_finished interrupt, cmd_phy_rx issued during preamble qualification 339.5 249 from rising edge of cs to cmd_finished interrupt, cmd_phy_rx issued during sync word qualification 346 252 from rising edge of cs to cmd_finished interrupt, cmd_phy_rx issued during rx data (after a sync word) 1 t paramp_down = t paramp_up = 100 ) (9 2 ? data_rate pa_ramp cr pa_level_m , where pa_level_mcr sets the maximum pa output power (pa_level_mcr register, address 0x307), pa_ramp sets the pa ramp rate (radio_cfg_8 register, address 0x114), and data_rate sets the transmit data rate (radio_cfg_0 register, address 0x10c and radio_cfg_1 register, address 0x10d). 2 t bit = one bit period ( s), t byte = one byte period ( s), t eop = time to end of packet ( s).
data sheet adf7023 rev. c | page 43 of 112 packet mode the on - chip communications processor can be configured for us e with a wide variety of packet -b ased radio pro tocols using 2 fsk/gfsk/msk/gmsk/ ook modulation. the general packet format, when using the packet management features of the communications processor, is illustrated in table 14. to us e the packet management features , the data _ mode setting in the packet_length_control re gister ( address 0x126) should be set to packet mode ; 240 bytes of dedicated packet ram are available to store , transmit , and receive packets. in transmit mode , preamble, sync word , and crc can be added by the communications processor to the data stored in the packet ram for transmission. in addition, all packet data after the sync word can be optionally whitened, manchester encoded , or 8b/10b encoded on transmission and decoded on reception. in receive mode , the communications processor can be used to qual ify received packets based on the preamble detection, sync word detection, crc detection , or address match and generate an interrupt on the irq_gp3 pin. on reception of a valid packet , the received payload data is loaded to packet ram memory. more information on interrupts is contained in the interrupt generation section. preamble the preamble is a mandatory part of the packet that is auto - matically added by th e communications processor when transmitting a packet and removed after receiving a packet. the preamble is a 0x55 sequence, with a programmable length between 1 byte and 256 bytes , that is set in the preamble_len register (address 0x11d). it is necessar y to have preamble at the beginning of the packet to allow time for the receiver agc, afc, and clock and data recovery circuitry to settle before the start of the sync word. the required preamble length depends on the radio configuration. see the radio blocks section for more details. in receive mode, the adf7023 can use a preamble qualification circuit to detect preamble and interrupt the host processor. the preamble qualification circuit tracks the received frame as a sliding window. the window is three bytes in length, and the preamble pattern is fixed at 0x55. the preamble bits are examined in 01pairs. if either bit or both bits are in error, the pair is deemed erroneous. the possible erroneous pairs are 00, 11, and 10. the number of erroneous pairs tolerated in the preamble can be set using the preamble_match register value (address 0x11b) according to table 13 . table 13 . preamble detection tolerance (preamble_ match, address 0x11b) value description 0x0c no errors allowed . 0x0 b one erroneous bit - pair allowed in 12 bit - pairs. 0x0 a two erroneous bit - pairs allowed in 12 bit - pairs. 0x09 three erroneous bit - pairs allowed in 12 bit - pairs. 0x0 8 four erroneous bit - pairs allowed in 12 bit - pairs. 0x00 preamble detection disabled. table 14 . adf7023 packet structure description 1 packet format options packet structure preamble sync payload crc postamble length address payload data field l ength 1 byte to 256 b ytes 1 bit to 24 bits 1 byte 1 byte to 9 bytes 0 bytes to 240 bytes 2 bytes 2 bytes optional f ield in packet structure x x yes yes yes yes x comm s p rocessor adds in t x , r emove s in rx y es yes x x x yes yes host w rites t hese f ields to p acket ram x x yes yes yes x x whitening/d e whitening (o ptional) x x yes yes yes yes x manchester encoding/ decoding (optional) x x yes yes yes yes x 8b/10b encoding/decoding (optional) x x yes yes yes yes x configurable parameter yes yes yes yes yes yes x receive interrupt on valid field detection yes yes x yes x yes x programmable field error tolerance yes yes x x x x x programmable field offset (see figure 78 ) x x x yes x x x 1 yes indicates that the packet format option is supported; x indicates that the packet format option is not supported.
adf7023 data sheet rev. c | page 44 of 112 if preamble _ match is set to 0x0c , the adf7023 must receive 12 consecutive 01 pairs ( three bytes) to confirm that valid preamble has been detected. the user can select the option to automatically lock the afc and/or agc once the qualified preamble is detected . the afc lock on preamble detection can be enabled by setting afc _ lock _ mode = 3 in the radio_cfg_10 register ( address 0x116:). the agc lock on preamble detection can be enabled by setting agc _ lock _ mode = 3 in the radio_cfg_7 register (a d dress 0x113 ). after the preamble is detected and the end of preamble has been reached , the communications processor searches for the sync word. the search for the sync word lasts for a duration equal to the sum of the number of programmed sync word bits, plus the preamble matching tolerance (in bits) plus 16 bits . if the sync word routine is detected during this duration , the c ommunications processor load s the received payload to packet ram and compute s the crc (if enabled). if the sync word routine is not detected during this duration , the communications processor continue s searching for the preamble. preamble de tection can be disabled by setting the preamble _ match register to 0x00. to enable an interrupt upon preamble detection, the user must set interrupt _ preamble _ detect =1 in the interrupt_mask_0 register ( address 0x100 ). s ync word sync word is the synchronization word used by the receiver for byte level synchronization, while also providing an optional interrupt on detection. it is automatically added to the packet by the communications processor in transmit mode and removed during reception of a packet. the value of the sync word is set in the sync _ byte_0, sync _ byte_1 , and sync _ byte_2 registers ( address 0x121, address 0x122 , and address 0x123 , respectively ) . the sync word is transmitted most significant bit first starting with sync _ byte _0 . the sync word matching length at the receiver is set using sync _ word _ length in the sync_control register (address 0x120) and can be one bit to 24 bits long; the transmitted sync word is a multiple of eight bits. therefore, for non byte length sync words, the transmitted sync pattern should be appended with the preamble pattern as described in figure 76 and table 16. in receive mode, the adf7023 can provide an interrupt on reception of the sync word sequence programmed in the sync _ byte_0, sync _ byte _1 , and sync _ byte _2 registers. this feature can be used to alert the host processor that a qualified sync word has been received. an error tolerance parameter can also be programmed that accepts a valid match when up to three bits of the sync word sequence are incorrect. the error tole rance value is set using the sync _ error _ tol setting in the sync_control register ( address 0x120) , as described in table 15. table 15 . sync wor d detection t olerance ( sync _ error _ tol , address 0x120) value description 00 no bit errors allowed . 01 one bit error allowed. 10 two bit errors allowed . 11 three bit errors allowed . figure 76 . transmit s ync w ord configuration sync_byte_2 sync_byte_1 sync_byte_0 24 bits sync_word_length > 16 bits append unused bits with preamble (0101..) fir s t bit sent msb lsb sync_byte_2 sync_byte_1 16 bits sync_word_length > 8 bits append unused bits with preamble (0101..) msb lsb sync_byte_2 sync_word_length 8 bits append unused bits with preamble (0101..) msb lsb 08291-068
data sheet adf7023 rev. c | page 45 of 112 table 16 . sync word p rogramming e xamples required sync w ord ( binary, f irst b it b eing f irst in t ime ) sync _ word _ length bits in sync_con trol register (0x120) sync_ byte _ 0 1 sync _ byte _1 1 sync _ byte _2 transmitted s ync w ord (binary, first bit b eing f irst in t ime) receiver sync word m atch length (b its) 000100100011010001010110 24 0x12 0x34 0x56 0001_0010_0011_0100_0101_0110 24 111010011100101000100 21 0x 5d 0x39 0x44 0101_1101_0011_1001_0100_0100 21 0001001000110100 16 0xxx 0x12 0x34 0001_0010_0011_0100 16 011100001110 12 0xxx 0x 57 0x0e 0101_0111_0000_1110 12 00010010 8 0xxx 0xxx 0x12 0001_0010 8 011100 6 0xxx 0xxx 0x 5c 0101_1100 6 1 x = dont c are. choice of s ync w ord the sync word should be chosen to have low correlation with the preamble and have good auto correlation properties. when the afc is set to lock on detection of sync word (afc_lock_ mode = 3 and preamble_match = 0) , the sync word should be chosen to be dc free , and it should have a run length limit not greater than four bits. payload the host processor writes the transmit data payload to the packet ram. the lo cation of the transmit data in the packet ram is defined by the tx_base _ adr value register ( address 0x124) . the tx _ base _ adr value is the location of the first byte of the transmit payload data in the packet ram. on reception of a valid sync word, the communications processor automatically loads the receive payload to the packet ram. the rx _ base _ adr register value ( address 0x125) sets the location in the packet ram of the first byte of the received payload. for more details on packet ram memory, see th e adf7023 memory map s ection. byte orientation the over - the - air arrangement of each transmitted packet ram byte can be set to msb first or lsb first using the data _ byte setting in the packet_length_control register ( address 0x126 ). the same orientation setting should be used on the transmit and receive side s of the rf link. packet length modes the adf7023 can be used in both fixed and variable length packet systems. fixed or variable length packet mode is set using the pac ket _ len variable setting in the packet_ length_control register (address 0x126) . for a fixed packet length system , the length of the transmit and received payload is set by the pac ket _ length _ max reg ister ( address 0x127). the payload length is defined as the number of bytes from the end of the sync word to the start of the crc. in variable packet length mode , the communications processor extracts the length field from the received payload data. in transmit mode , t he length field must be the first byte in the transmit payload. the communications processor calculates the ac tual received payload length as rxpayload l ength = l ength + length_offset ? 4 where: l ength is the length field ( the first byte in the received payload) . length_offset is a programmable offset (set in the pac ket_ length_control register (address 0x126) . the length_offset value allow s compatibility with systems where the length field in the proprietary packet may also in clude the length of the crc and/or the sync word. the adf7023 defines the payload length as the number of bytes from the end of the sync word to the start of the crc. in variable packet length mode , the pac ket _ length _ max value defines the maximum packet le ngth that can be received , as described in figure 77 . figure 77 . payload l ength in f ixed and v ariable l ength packet m odes addressing the adf7023 provides a very flexible address matching scheme , allowing matching of a single address, multiple addresses , and broadcast addresses. addresses up to 32 bits in length are supported. the address information can be included at any section of the tra nsmit payload. the location of the starting byte of the address data in the received payload is set in the address _ match _ offset register ( address 0x129) , as illustrated in figure 78 . the number of bytes in the first address field is set in the address_length register (address 0x12a ) . these settings allow the communications processor to extract the address information fro m the received packet. 08291-125 fixed tx pa yload length = p acket_length_max rx pa yload length = p acket_length_max tx pa yload length = length rx pa yload length = length + length_offset C 4 preamble sync word length v ariable pa yload crc preamble sync word pa yload crc
adf7023 data sheet rev. c | page 46 of 112 the address data is then compared against a list of known addresses that are stored in bbram ( address 0x12 b to address 0x13 7 ). each stored address byte has an associated mask byte , thereby allowing matching of partial sections of the address bytes, which is useful for checking broadcast addresses or a family of addresses that have a unique identifier in the address sequence. the format and placement of the address information in the payload data should match the address check setti ngs at the receiver to ensure exact address detection and qualification. table 17 s hows the register locations in the bbram that are used for setup of the address checking. when r egister 0x12a (number of bytes in the first address field) is set to 0x00 , a ddress checking is disabled. note that if static register fixes are employed (see table 91 ), the space available for address matching is reduced. figure 78 . address match offset table 17. address check register setup address (bbram) description 1 0x129, address _ match _ offset position of first address byte in the received packet (first byte after sync word = 0) 0x12 a, address_ length number of b ytes in the first a ddress field (n adr _ 1 ) 0x12 b address m atch b yte 0 0x12 c address m ask b yte 0 0x12 d address m atch b yte 1 0x12e address m ask b yte 1 address m atch b yte n adr _ 1 ? 1 address m ask b yte n adr _ 1 ? 1 0x00 to end or n adr _2 for another address check sequence 1 n adr _1 = the number of byte s in the first address fiel d; n adr _2 = the number of byte s in the second address field . the host processor should set the interrupt _ address _ match bit in the interrupt_source_0 register (address 0x336) if an interrupt is required on the ir q _gp3 pin. additional information on interrupts is contained in the interrupt generation section. example address check consider a system with 16 - bit address lengths, in which the firs t byte is located in the 10 th byte of the received payload data. the system also uses broadcast addresses in which the first byte is always 0xaa. to match the exact address, 0xabcd or any broadcast address in the form 0xaaxx , the adf7023 must be configured as shown in table 18. table 18 . example address check configuration bbram address value d escription 0x129 0x09 location in payload of the first address by te 0x12a 0x0 2 number of bytes in the first address field, n adr _ 1 = 2 0x12b 0xab address match byte 0 0x12c 0xff address mask byte 0 0x12d 0xcd address match byte 1 0x12e 0xff address mask byte 1 0x12f 0x02 number of bytes in the second address field, n adr_2 = 2 0x130 0xaa address match byte 0 0x131 0xff address mask byte 0 0x132 0x00 address match byte 1 0x133 0x00 address mask byte 1 0x134 0x00 end of addresses (indicated by 0x00) 0x135 0xxx dont care 0x136 0xxx dont care 0x137 0xxx dont care crc an optional crc - 16 can be appended to the packet by setting crc _ en =1 in the packet_length_control register (address 0x126). in receive mode , this bit enables crc detection on the received packet. a defaul t polynomial is used if prog _ crc _ en = 0 in the symbol _ mode register (address 0x11c) . the default crc polynomial is g ( x ) = x 16 + x 12 + x 5 +1 any other 16 - bit polynomial can be used if prog _ crc _ en = 1, and the polynomial is set in crc _ poly _0 and crc _ poly _1 ( address 0x11e and address 0x11f , respectively ). the setup of the crc is described in table 19. the crc is initialized with 0x0000. table 19 .crc s etup crc _ en bit in the packet_ length control register prog _ crc _ en bit in the symbol_ mode register description 0 x 1 crc is disabled in transmit , and crc detection is disabled in receive . 1 0 crc is enabled in transmit , and crc detection is enabled in receive, with the default crc polynomial . 1 1 crc is enabled in transmit , and crc detection is enabled in receive, with the crc polynomial defined by crc _ poly _0 and crc _ poly _1 . 1 x = dont care. 08291-126 address_m a tch_offset preamble sync word address dat a pa yload crc
data sheet adf7023 rev. c | page 47 of 112 t o convert a user - defined polynomial to the 2- byte value, the polynomial should be written in binary format . the x 16 coefficient is assumed equal to 1 and is , therefore , discarded. the remaining 16 bits then make up crc _ poly _0 ( most significant byte ) and crc _ poly _1 ( least significant byte ). two examples of setting common 16 - bit crc s are shown in table 20. table 20. example: programming of crc _ poly_0 and crc _ poly_1 polynomial binary format crc_poly_0 crc_poly_1 x 16 + x 15 + x 2 + 1 (crc -16 - ibm) 1_1000_0000_ 0000_0101 0x80 0x05 x 16 + x 13 + x 12 + x 11 x 10 + x 8 + x 6 + x 5 + x 2 + 1 (crc -16 - dnp) 1_ 00 11 _ 11 0 1_ 0 110_0101 0x3d 0x65 to enable crc detection on the receive r, with the default crc or user - defined 16 - bit crc , crc _ en in the packet_ length_control register ( address 0x126 ) s hould be set to 1. an interrupt can be generated on reception of a crc verified packet ( see the interrupt generation section). postamble the communications processor automatically appends two bytes of post amble to the end of the transm itted packet. each byte of the post amble is 0x55. the first byte is transmitted immedia tely after the crc. the pa ramp - down begins i mmediately after the first post amble byte. the second byte is transmitted while the pa is ramping down. on the receiver, if the received packet is v alid, the rssi is automatically measured during the first post amble byte , and the result is stored in the rssi _ readback register ( address 0x312). the rssi is measured by the communications processor 17 s after the last crc bit. transmit packet timi ng the pa ramp timing in relation to the transmit packet data is described in figure 79. after the cmd_phy_tx command is issued, a vco calibration is carried out , followed by a delay for synthesizer settling. the pa ramp follows the synthesizer settling. after the pa is ramped u p to the programmed rate, there is 1 - byte delay before the start of modulation (preamble). at the begin ning of the second byte of post amble , the pa ramps down. the communications processor then transitions to the phy_on state or the phy_rx state (if the tx _ auto _ turn _ around bit is enabled or the cmd_phy_rx command is issued). figure 79 . transmit p acket t iming 142s 55s vco ca l synth preamble sync word crc post amble pa yload phy_tx = 0x14 (phy_tx) = 0x00 (busy) pa ram p pa ram p 1 byte ram p time ram p time sta te transition time to phy_tx (see t able 12) cmd_phy_tx pa output tx d at a communic a tions processor fw_s ta te 08291-127
adf7023 data sheet rev. c | page 48 of 112 data whitening data whitening can be employed to avoid long runs of 1 s or 0s in the transmitted data stream. this ensures sufficient bit transitions in the packet, which aids in receiver clock and data recovery because the encoding breaks up long runs of 1 s or 0s in the transmit packet. the data, excluding the preamble and sync word, is automatically whit ened before transmission by xor ing the data with an 8 - bit pseudorandom sequence. at the receiver, the data is xored with the same pseudo random sequence, thereby reversi ng the whitening. the linear feedback shift register polynomial used is x 7 + x 1 + 1. data whitening and de whitening are enabled by setting data _ whitening = 1 in the symbol_mode register ( address 0x11c ). manchester encoding manchester encoding can be u s ed to ensure a dc - free (zero mean) transmission. the encoded over - the - air bit rate (chip rate) is double the rate set by the data _ rate variable ( address 0x10c and address 0x10d). a b inary 0 is mapped to 10, and a b inary 1 is mapped to 01. manchester encodi ng and decoding are applied to the payloa d data and the crc. it is recommended to use manchester e ncoding for ook modu - lation. manchester encoding and decoding are enabled by setting manchester _ enc = 1 in the symbol_mode register (address 0x11c). 8b/10b encoding 8b/10b encoding is a byte - orientated encoding scheme that maps an 8 - bit byte to a 10 - bit data block. it ensures that the maximum number of consecutive 1 s or 0 s ( that is, run length) in any 10 - bit transmitted symbol is five . the advantage of this encoding scheme is that dc balancing is employed without the efficiency loss of man chester encoding. the rate loss for 8b/10b encoding is 0.8, wh ereas for manchester encoding , it is 0.5. encoding and decoding are applied to the payl oad data and the crc. the 8b/10b encoding and decoding are enabled by setting eight _ ten _ enc =1 in the symbol_ mode register (address 0x11c).
data sheet adf7023 rev. c | page 49 of 112 sport mode it is possible to bypass all of the packet management features of the adf7023 and use the sport interface for transmit and receive data. the sport interface is a high speed synchronous serial interface allowing direct interfacing to processor s and dsps. s port mode is enabled using the data _ mode set ting in the pac ket _ length _ control register ( address 0x126) , as described in table 21. the sport mode interface is on the gpio pins (gp0, gp1, gp2, gp4 , and xosc32kp _gp5_atb1 ). these gpio pins can be configured using the gpio _ configure setting ( address 0x3fa) , as described in table 22 . s port mode provides a receive interrupt sour ce on gp4. this interrupt source can be configured to provide an interrupt, or strobe signal, on either preamble detection or sync word detection. the type of interrupt is configured using the gpio _ configure setting. packet structure in s port mode in sport mode , the host processor has full control over the packet structure. however, the preamble frame is still required to allow sufficient bits for receiver settling (agc, afc , and cdr). in sport mode , sync word detection is not mandatory in the adf7023 but c an be enabled to provide byte level sy nchronization for the host processor via the sync word detect interrupt or strobe on gp4. the general format of a sport mode packet is shown in figure 80 . figure 80 . general s port m ode p acket s port mode in transmit figure 81 ill ustrates the operation of the sport interface in transmit. once in the phy_tx state with sport mode enabled, the data input of the transmitter is fully controlled by the sport interface (p in gp1) . the transmit clock appears on the gp2 pin. the t ransmit data from the host processor should be synch - ronized with this clock. the fw _ state variable in the status word or the cmd _ finished interrupt can be used to indicate when the adf7023 has reached the phy_tx state and , there - fore , is ready to begin tr ansmitting data. the adf7023 keeps transmitting the serial data presented at the gp1 input until the host processor issues a command to exit the phy_tx state. s port mode in receive the sport interface supports the receive operation with a number of modes t o suit particular signaling requirements. the receive data appears on the gp0 pin , wh ereas the receive synch ronized clock appears on the gp2 pin. the gp4 pin provides an interrupt or strobe signal on either preamble or sync word detection , as described in table 21 and table 22. once enabled , the interrupt signal and strobe signals remain operational while in the phy_rx state . the strobe signal gives a single high pulse of 1 - bit duration every eight bits. the strobe signal is most useful when used with sync word detection because it is synchro nized to the sync word and strobes the first bit in every byte. transmit bit latenci es in s port mode the transmit bit latency is the time from the sampling of a bit by the transmit data clock on gp2 to when that bit appears at the rf output. there is no tr ansmit bit latency when using 2 fsk/msk modulation. the latency when using gfsk/gmsk modulation is two bits. it is important that the host p rocessor keep the adf7023 in the phy_tx state for two bit periods after the last data bit is sampled by the data cloc k to account for this latency when using gmsk/gfsk modulation. table 21 . sport mode s etup data _ mode bits in packet_length_ control register description gpio configuration data _ mode = 0 packet m ode enabled. packet management is controlled by the communications processor. data _ mode = 1 s port mode enabled. the rx data and rx clock are enabled in the phy_rx state ( gpio _ configure = 0xa0, 0xa3, 0xa6) . the rx clock is enabled in the phy_rx state, and rx data is enabled on the preamble detect ( gpio _ configure = 0xa1, 0xa2, 0xa4, 0xa5, 0xa7, 0xa8) . gp0: rx d ata gp1: tx d ata gp2: tx/rx cl ock gp4: interrupt or strobe enabled on preamble detect (depends on gpio _ configure ) xosc32kp_gp5 _atb1 : depends on gpio _ configure data _ mode = 2 s port mode enabled. the rx data and rx clock are enabled in the p hy_rx state if gpio _ configure = 0xa0, 0xa3, 0xa6. the rx clock is enabled in the phy_rx state, and rx data is enabled on the preamble detect if gpio _ configure = 0xa1, 0xa2, 0xa4, 0xa5, 0xa7, 0xa8 . gp0: rx d ata gp1: tx d ata gp2: tx/rx c lock gp4: interrupt or strobe enabled on sync word detect (depends on gpio _ configure ) xosc32kp_gp5 _atb1 : depends on gpio _ configure 08291-128 preamble sync word pa yload
adf7023 data sheet rev. c | page 50 of 112 table 22 . gpio f unctionality in s port mode gpio _ configure gp0 gp1 gp2 gp4 xosc32kp_gp5_atb1 0xa0 rx d ata tx d ata tx/rx c lock n ot used n ot used 0xa1 rx d ata tx d ata tx/rx c lock interrupt n ot used 0xa2 rx d ata tx d ata tx/rx c lock strobe n ot used 0xa3 rx d ata tx d ata tx/rx c lock n ot used 32.768 khz x tal input 0xa4 rx d ata tx d ata tx/rx c lock interrupt 32.768 khz x tal input 0xa5 rx d ata tx d ata tx/rx c lock strobe 32.768 khz x tal input 0xa6 rx d ata tx d ata tx/rx c lock n ot used ext _ uc _ clk output 0xa7 rx d ata tx d ata tx/rx c lock interrupt ext _ uc _ clk output 0xa8 rx d ata tx d ata tx/rx c lock strobe ext _ uc _ clk output figure 81 . s port mode t ransmit figure 82 . s port mode r eceive, data _ mode = 1, 2 and gpio _ configure = 0xa0, 0 x a3, 0xa6 preamble sync word pa yload pa ram p pa ram p phy_tx cmd_phy_on cmd_phy_tx p acket irq_gp3 (cmd_finished interrupt) gp2 (tx clk) gp0 (tx d at a) gp2 (tx clk) gp1 (tx d at a) 08291-129 preamble sync word pa yload phy_rx cmd_phy_on cmd_phy_rx p acket gp4 gp2 (rx clk) gp0 (rx d at a) gp2 (rx clk) gp0 (rx d at a) 08291-130
data sheet adf7023 rev. c | page 51 of 112 figure 83 . sport mode receive , data _ mode = 1, gpio _ configure = 0xa1, 0xa2, 0xa4, 0xa5, 0xa7, 0xa8 figure 84 . s port m ode r eceive, data _ mode = 2, gpio _ configure = 0xa1, 0xa2, 0xa4, 0xa5, 0xa7, 0xa8 preamble sync word preamble detected pa yload phy_rx cmd_phy_on cmd_phy_rx p acket gp4 (gpio_configure = 0xa1) gp4 (gpio_configure = 0xa2) gp2 (rx clk) gp0 (rx d at a) gp4 (gpio_configure = 0xa1) gp4 (gpio_configure = 0xa2) gp2 (rx clk) gp0 (rx d at a) 8/(d at a r ate) 08291-131 preamble sync word swd bit n-9 swd bit n-8 swd bit n-7 swd bit n-6 swd bit n-5 swd bit n-4 swd bit n-3 swd bit n-2 swd bit n-1 swd bit n pa yload bit 1 pa yload bit 2 pa yload phy_rx cmd_phy_on cmd_phy_rx p acket gp4 (gpio_configure = 0xa1) gp4 (gpio_configure = 0xa2) gp2 (rx clk) gp0 (rx d at a) gp4 (gpio_configure = 0xa1) gp4 (gpio_configure = 0xa2) gp2 (rx clk) gp0 (rx d at a) 08291-132
adf7023 data sheet rev. c | page 52 of 112 interrupt generation t he adf7023 uses a highly flexib le, powerful interrupt system with support for mac level interrupts and phy level interrupts . to enable an interrupt sourc e, the corresponding mask bit must be set. when an enabled interrupt occurs, the irq_gp3 pin go es high , and the interrupt bit of the status word is set to l ogic 1. the host processor can use either the irq_gp3 pin or the status word to check for an interrupt. after an interrupt is asserted, the adf7023 continues operation s unaffected , unless it is directed to do oth erwise by the host processor. an outline of the interrupt source and mask system is shown in table 23 . mac interrup ts can be enabled by writing a l ogic 1 to the relevant bits of the interrupt _ mask _0 register ( address 0x100) and phy level interrupts by writing a l ogic 1 to the relevant bits of the interrupt _ mask _1 register (address 0x101). the structure of these memory locations is described in table 23 . in the case of an interrupt condition, the interrupt source can be determined by reading the interrupt _ source _0 register ( address 0x336) and the interrupt _ source _1 register (ad dress 0x337) . the bit that corresponds to the relevant interrupt condition is high. the structure of these two registers is shown in t able 24 . following an int errupt condition, the host processor should clear the relevant interrupt flag so that further interrupts assert the irq_gp3 pin. this is performed by writing a l ogic 1 to the bit that is high in either the interrupt _ source _0 or interrupt _ source _1 register. if multiple bits in the interrupt source registers are high, they can be cleared individually or altogether by writing l ogic 1 to them. the irq_gp3 pin go es low when all the interrupt source bits are cleared. as an example, take the case where a battery alarm (in the interrupt_source_1 register) interrupt occurs . the host processor should 1. read the i nterrupt s ource registers . in this example , if none of the interrupt flags in interrupt _ source _0 is enabled, only interrupt _ source _1 must be read. 2. clea r the interrupt by writing 0x80 (or 0xff) to interrupt _ source _1 . 3. respond to the interrupt condition . table 23. structure of the i nterrupt mask r egisters register bit name description interrupt_mask_0 , address 0x100 7 interrupt_num_wakeups interrupt when the number of wuc wake - ups (number_of_wakeups[15:0]) has reached the threshold (number_of_wakeups_irq_threshold[15:0]) 1: i nterrupt enabled; 0: i nterrupt disabled 6 interrupt_swm_rssi_det interrupt when the measured rssi during smart wake mode has exceeded the rssi threshold value (s wm _rssi_thres h , address 0x108) 1: i nterrupt enabled; 0: i nterrupt disabled 5 interrupt_aes_done interrupt when an aes encryption or decryption command is complete; a vailable only when the aes firmware module has been loaded to the adf7023 program ram 1: i nterrupt enabled; 0: i nterrupt disabled 4 interrupt_tx_eof interrupt when a packet has finished transmitting 1: i nterrupt enabled; 0: i nterrupt disabled 3 interrupt_address_match interrupt when a received packet has a valid address match 1: i nterrupt enabled; 0: i nterrupt disabled 2 interrupt_crc_correct interrupt when a received packet has the correct crc 1: i nterrupt enabled; 0: i nterrupt disabled 1 interrupt_sync_detect interrupt when a qualified sync word has been detected in the received packet 1: i nterrupt enabled; 0: i nterrupt disabled 0 interrupt_preamble_detect interrupt when a qualified preamble has been detected in the received packet 1: i nterrupt enabled; 0: i nterrupt disabled
data sheet adf7023 rev. c | page 53 of 112 register bit name description interrupt_mask_ 1, address 0x10 1 7 battery_alarm interrupt when the b at tery voltage has dropped below the threshold value ( battery_monitor_threshold_voltage , address 0x32d) 1: i nterrupt enabled; 0: i nterrupt disabled 6 cmd_ready interrupt when the communications processor is ready to load a new command ; mirrors the cmd_ready bit of the status wor d 1: i nterrupt enabled; 0: i nterrupt disabled 5 reserved 4 wuc_timeout interrupt when the wuc has timed out 1: i nterrupt enabled; 0: i nterrupt disabled 3 reserved 2 reserved 1 spi_ready interrupt when the spi is ready for access 1: i nterrupt enabled; 0: i nterrupt disabled 0 cmd_finished interrupt when the communications processor ha s finished performing a command 1: i nterrupt enabled; 0: i nterrupt disabled t able 24 . structure of the interrupt so urce r egisters register bit name interrupt description interrupt _ source _0 , address: 0x336 7 interrupt _ num _ wakeups asserted when the number of wuc wake - ups ( number _ of _ wakeups [15:0]) has reached the threshold ( number _ of _ wakeups _ irq _ threshold [15:0]) . 6 interrupt _ swm _rssi_ det asserted when the measured rssi during smart wake mode has exceeded the rssi threshold value (s wm _rssi_thres h , address 0x108) . 5 interrupt _ aes_ done asserted when an aes encryption or decryption command is complete; a vailable only when the aes firmware module has been loaded to the adf7023 program ram . 4 interrupt _ tx _ eof asserted when a packet has finished transmitting (packet mode only) . 3 interrupt _ address _ match asserted when a received p acket has a valid address match (packet mode only) . 2 interrupt _ crc _ correct asserted when a received packet has the correct crc (packet mode only) . 1 interrupt _ sync _ detect asserted when a qualified sync word has been detected in the received packet . 0 interrupt _ preamble _ detect asserted when a qualified preamble has been detected in the received packet . interrupt _ source _1 , address: 0x337 7 bat tery _ alarm asserted when the b at tery voltage has dropped below the threshold value ( battery_monitor_threshold_voltage , address 0x32d) . 6 cmd _ ready asserted when the c ommunications processor is ready to load a new command ; m irrors the cmd _ ready bit of the status word . 5 reserved 4 wuc _ timeout asserted when the wuc has timed out . 3 reserved 2 reserved 1 spi_ ready asserted when the spi is ready for access . 0 cmd _ finished asserted when the c ommunications processor has finished performing a command . if the cmd_finished interrupt is enabled, following the issue of cmd_phy_tx, the first bit of user data is transmitted 1.5 t bit + 2.3 s following the interrupt. the pa ramp start s 3.4 s after the interrupt. (t bit is the time taken to transmit one bit.) interrupts in sport mode in sport mode , the interrupts from interrupt _ source _1 are all available. however , only interrupt _ preamble _ detect and interrupt _ sync _ detect are available from interrupt _ source _0. a second interrupt pin is provided on gp4 , which gives a dedicated sport mode interrupt on either preamble or sync word detection. for more details , see the sport mode section .
adf7023 data sheet rev. c | page 54 of 112 adf7023 memory map figure 85 . adf7023 memory map this section describes the various memory locations used by the adf702 3 . the radio control, packet management , and smart wake mode capabilities of the part are realized through the use of an integrated risc processor , which execute s instructions stored in the embedded program rom. there is also a local ram, subdivided into three sections, that is used as a data packet buffer, both for transmitted and received data (packet ram) , and for storing the radio and packet management configuration (bbram and mcr). the ram addresses of these memory banks are 11 bits long . bbram the battery backup ram (bbram) contains the main radio and packet m anagement registers used to configure the radio. on application of battery power to the adf7023 for the first time , the entire bbram should be initialized by the host processor with the appropriate settings. after the bbram has been written to , the cmd_con fig_dev command should be issued to update the radio and communication s processor with the current bbram settings. the cmd_config_dev command can be issued in the phy_off state or the phy_on state only . the bbram is used to maintain settings needed at wak e- up from sleep mode by the wake - up controller . upon wake - up from sleep, in smart wake mode, the bbram contents are read by the on - chip processor to recover the packet management and radio parameters. modem configuration ram (mcr) the 256 - byte modem confi guration ram ( mcr ) contains the various registers used for direct control or observation of the physical layer radio blocks of the adf702 3. the co ntents of the mcr are not retained in the phy_sleep state. program rom the program rom consists of 4 kb of non volatile memory. it contains the firmware code for radio control, packet manage - ment , and smart wake mode. program ram the program ram consists of 2 kb of volatile memory. this memory space is used for software modules, such as aes en - cryption, ir c alibration , and reed solomon coding , which are available from a nalog devices . the software modules are down - loaded to the program ram memory space over the spi by the host processor. see the downloadable firmware modul es section for details on loading a firmware module to program ram. 08291-070 spi cs miso mosi sclk data[7:0] address[10:0] not used reserved 0x100 0x13f 0x300 0x3ff 0x0ff 0x000 0x00f 0x000 address [12:0] program ram 2kb program rom 4kb mcr 256 bytes bbram 64 bytes packet ram 256 bytes instruction/data [7:0] 11-bit addresses address/ data mux spi/cp memory arbitration comms processor clock comms processor 8-bit risc engine
data sheet adf7023 rev. c | page 55 of 112 packet ram the p acket ram consists of 256 bytes of memory space. the first 16 bytes of this memory space are allocated for use by the on - chip processor. the remaining 240 bytes of this memory space are allocated for storage of data from valid received packets and packet d ata to be transmitted. th e communications processor store s received payload data at the memory location indicated by t he value of the rx _ base _ adr register (address 0x125) , the receive address pointer . t he value of the tx _ base _ adr register (address 0x124) , the transmit address pointer, determines the start ad dress of data to be transmitted by the communications processor. this memory can be arbitrarily assigned to store single or multiple t ransmit or receive packets, with and without overlap. the rx _ base _ adr value should be chosen to ensure that there is enough allocated packet ram space for the maximum receiver payload length. figure 86 . example packet ram configurations u sing the tx packet and r x p acket a ddress p ointers transmit or receive pa yload transmit pa yload receive pa yload transmit pa yload receive pa yload receive pa yload 2 transmit pa yload 2 mul tiple transmit and receive p ackets 240 byte transmit or receive p acket transmit and receive p acket 0x010 0x0ff 0x010 0x0ff 0x010 0x0ff tx_base_adr (p acket 1) tx_base_adr rx_base_adr tx_base_adr rx_base_adr tx_base_adr (p acket 2) rx_base_adr (p acket 1) rx_base_adr (p acket 2) 08291-071
adf7023 data sheet rev. c | page 56 of 112 spi interface general characterist ics the adf702 3 is equipped with a 4 - wire spi interface, using the sclk, miso, mosi, and cs pins. the adf7023 always acts as a slave to the host proc essor. figure 87 shows an example connection diagram between the processor and the adf702 3 . the diagram also shows the direction of the signal flow fo r each pin. the spi interface is active , and the miso output s enabled , only while the cs input is low. the interface uses a word length of eight bits, which is compatible with the spi hardware of most processors. the data transfer through the spi interface occurs with the most significant bit first. the mosi input is sampled at the rising edge of sclk. as commands or data are shifted in from the mosi input at the sclk rising edge, the status word or data is shifted out at the miso pin synchronous with the sclk clock falling edge. if cs is brought low, the most significant bit of the status word appears on the miso output without the need for a rising clock edge on the sclk input. figure 87 . spi i nterface connections command access the adf702 3 is controlled through commands. command words are single octet instructions that control the state transitions of the communications processor and access to the registers and packet ram. the complete list of valid commands is given in the command reference section. commands that have a cmd prefix are handled by the communications processor . memory access commands have an spi prefix and are handled by an independent controller. thus, spi commands can be issued independent of the state of the communications processor. a command is initiated by bringing cs low and shifting in the command word over the spi , as shown in figure 88 . all commands are executed on the last positive sclk edge of the command . the cs input must be brought hi gh again after a command has been shifted into the adf7023 to enable the recognition of successive command words . this is because a single command can be issued only during a cs low period (with the exception of a double nop command). figure 88 . co mmand w rite (no p arameters) status w ord the status word of the adf7023 is automatically returned over the miso each time a byte is transferred over the mosi. shifting in double spi_nop commands (see table 27 ) cause s the status word to be shifted out as shown in figure 89 . the meaning of the various bit fields is illustrated in table 25 . the fw_ state variable can be u sed to read the current state of the communications processor and is described in table 26 . if it is busy performing an action or state transition , fw _ state is busy. the fw _ state variable also indicates the current state of the radio. the spi_ready variable is used to indicate when the spi is ready for access. the cmd _ ready variable is used to indicate when the communications processor is ready to accept a new command . the status word should be polled and the cmd _ ready bit examined before issuing a command to ensure that the communications processor is ready to accept a new command. it is not necessary to check the cmd _ ready bit before issuing a spi memory acces s command. it is possible to queue one command while the communications processor is busy. this is discussed in the command queuing section. the adf7023 interrupt handler can be also be configured to generate an interrupt signal on irq_gp3 when the communi - cations processor is ready to accept a new command ( cmd _ ready in the interrupt_ source_1 register (address 0x337) ) or when it has finished processing a command ( cmd _ finished in the interrupt_ source_1 register (address 0x337)) . figure 89 . reading the status word using a double spi_nop command table 25 . status word bit name description [7] spi_r eady 0: spi is not ready for access . 1: spi is ready for access . [6] irq _s tatus 0: no pending interrupt condition . 1: pending interrupt condition (mirrors the irq_gp3 pin) . [5] cmd _ ready 0 : the r adio c ontroller is not ready to receive a radio controller command . 1: the r adio c ontroller is ready to receive a radio controller command . [4:0] fw _ state indicates the adf7023 state ( in table 26 ). adf7023 host processor sclk mosi miso irq_gp3 gpio sclk mosi miso irq 08291-026 cs cmd ignore cs mosi miso 08291-027 mosi cs miso spi_nop spi_nop ignore status 08291-028
data sheet adf7023 rev. c | page 57 of 112 table 26. fw _ state description value state 0x0f initializing 0x00 busy, pe rforming a state transition 0x11 phy_off 0x12 phy_on 0x13 phy_rx 0x14 phy_tx 0x06 phy_sleep 0x05 performing cmd_get_rssi 0x07 performing cmd_ir_cal 0x08 performing cmd_aes_ decrypt_init 0x09 performing cmd_aes_dec rypt 0x0a performing cmd_aes_enc rypt command queuing the cmd _ ready status bit is used to indicate that the command queue used by the communications processor is empty. the queue is one command deep. the fw _ state bit is used to indicate the state of the communications processor. the operation of the status word and these bits is illustrated in figure 90 when a cmd_phy_on command is issued in the phy_off state . o peration of the status word when a command is being queued is illustrated in figure 91 whe n a cmd_phy_on command is issued in the phy_off state followed quickly by a cmd_ phy_rx command. the cmd_phy _rx command is issued while fw_ state is busy ( that is, transitioning between the phy_off and phy _on states ) but the cmd _ ready bit is high , indicating that the command queue is empty. after the cmd_phy_rx command is issued , the cmd _ ready bit transitions to a logic low , indicating that the command queue is full . after the phy_off to phy_on transition is finished , the phy_rx command is processed immediately by the communications processor , and the cmd _ ready bit goes high, indicating that the command queue is empty and another command can be issued. figure 90 . operation of the cmd _ ready and fw _ state b its in t ransitioning the adf7023 from the phy_off state to the phy_on state figure 91 . command q ueuing and o peration of the cmd _ ready and fw _ state bits in tr ansitioning the adf7023 from the phy_off state to the phy_on state and then to the phy_rx state 08291-138 transition radio from phy_off t o phy_on w aiting for command w aiting for command 0xb2 = 0x12 (phy_on) 0xa0 0xb1 = 0x 1 1 (phy_off) = 0x00 (busy) issue cmd_phy_on 0x80 08291-138 cmd_read y fw_s ta te sta tus word communic a tions processor action cs transition radio from phy_on t o phy_rx transition radio from phy_off t o phy_on w aiting for command w aiting for command 0xb3 0xa0 0x80 0x80 0xa0 0xb1 = 0x 1 1 (phy_off) = 0x00 (busy) = 0x13 (phy_rx) = 0x00 (busy) 0x12 issue cmd_phy_on issue cmd_phy_rx 0xb2 08291-139 cmd_read y fw_s ta te sta tus word communic a tions processor action cs in phy_on, reading new command
adf7023 data sheet rev. c | page 58 of 112 memory access memory locations are accessed by invoking the relevant spi command. a n 11 - bit address is used to identify registers or locations in the memory space . the most significant three bits of the address are incorporated into the spi command by appending them as the lsb s of the command word . figure 92 illustrates command, address , and data partitioning. the various spi memory access commands are different , depending on the memory location being accessed (see table 27 ). an spi command should be issued only if the spi _ ready bit in the interrupt_source_1 register (address 0x337) of the status word bit is high. the adf7023 interrupt handler can be also be con figured to generate an interrupt signal on irq_gp3 when the spi_ready bit is high. a n spi command should not be issued while the communications processor is initializing ( fw_ state = 0x0f). spi commands can be issued in any other communications processor s tate , including the busy state ( fw_ state = 0x00). this allows the adf7023 memory to be accessed while the radio is transi - tioning between states. block write mcr, bbram , and p acket ram memory locations can be written to in block format using the spi_mem_wr command. the spi_mem_wr command code is 0 0011xxxb , where xxxb represent bits[10:8] of the first 11 - bit address. if more than one data byte is written, the write address is automatically incremented for every byte sent until cs is set high , which terminates the memory access command (s ee figure 93 for more details ). the maximum block write for the mcr, packet ram , and bbram memories is 256 bytes, 25 6 bytes , and 64 bytes , respectively. these maximum block - write lengths should not be exceeded. example write 0x00 to the adc _ config _ high register ( address 0x35a) . ? the first five bits of the spi_mem_wr command are 00011. ? the 11 - bit address of adc_ config _ high is 01101011010. ? the first byte sent is 00011011 or 0x1b. ? the second byte sent is 01011010 or 0x5a. ? the third byte sent is 0x00. thus, 0x1b , 0x 5a , 0x 00 is written to the part. figure 92 . spi mem ory access command/address format table 27. summary of spi m emory a ccess c ommands spi command command value description spi_mem_wr 0x18 (packet ram) 0x19 (bbram) 0x1b (mcr) 0x1 e (program ram) write data to bbram , mcr , or p acket ram sequentially. an 11 - bit address is used to identify memory locations. the most significant three bits of the address are incorporated in to the command (xxxb). this command is followed by the remaining eight bits of the address. spi_mem_rd 0x38 (packet ram) 0x39 (bbram) 0x3b (mcr) read data from bbram, mcr , or p acket r am sequentially. an 11 - bit address is used to identify memory locations. the most significant three bits of the address are incorporated into the command (xxxb). this command is followed b y the remaining eight bits of the address, which is subsequently followed by the appropriate number of spi_nop commands. spi_memr_wr 0x08 (packet ram) 0x09 (bbram) 0x0b (mcr) write data to bbram , mcr , or p acket ram non sequentially . spi_memr_rd 0x28 (packet ram) 0x29 (bbram) 0x2b (mcr) read data from bbram , mcr , or p acket ram non sequentially . spi_nop 0x ff no operation. use fo r dummy writes when polling the status word . a lso used as dummy data on the mosi line when performing a memory read. cs mosi spi memo ry access command memory address bits[7:0] dat a byte 5 bits memory address bits[10:0] dat a n 8 bits 08291-029
data sheet adf7023 rev. c | page 59 of 112 random address write mcr, bbram , and p acket ram memory locations can be written to in a nonsequential manner using the spi_memr_wr command . the spi_memr_wr command code is 0 000 1xxxb , where xxxb represent b its[10:8] of the 11 - bit address. the lower eight bits of the address should follow this command and then the data byte to be written to the address. the lower eight bits of the next address are entered , followed by the data for that address until all requi red addresses within that block are written, as shown in figure 94. program ram write the program ram can be written to only by using the memory block write , as i llustrated in figure 93. spi_mem _wr should be set to 0x1 e. see the downloadable firmware modules section for details on loading a firmware module to program ram. block read mcr, bbram , and p acket ram memory locations can be read from in block format using the spi_mem_rd command. the spi_ mem_rd command code is 0 01 11xxxb , where xxxb represent bits[10:8] of the first 11 - bit address. this command is followed by the remaining eight bits of the address to be read and then two spi_nop commands (dummy byte). the first byte available after writing the address should be ignored, with the second byte constituting valid data. if more than one data byte is to be read, the write address is automatically incremented for subsequent spi_nop commands sent. see figure 95 for more details. random address read mcr, bbram , and p acket ram memory loca tions can be read from memory in a non sequential manner using the spi_memr_rd command. the spi_memr_rd command code is 0 010 1xxxb , where xxxb represent bits[10:8] of the 11 - bit address. this command is followed by the remaining eight bits of the address to be written. each subsequent address byte is then written. the last address byte to be written should be follow ed by two spi_nop commands , as shown in figure 96. the data bytes from memory, starting at the first address location , are available after the second status byte. exa mple read the value stored in the adc_ config _ high register. ? the first five bits of the spi_mem_rd command are 00111. ? the 11 - bit address of adc_ config _ high is 01101011010. ? the first byte sent is 00111011 or 0x3b. ? the second byte sent is 01011010 or 0x5a. ? th e third byte sent is 0xff (spi_nop). ? the fourth byte sent is 0xff. thus, 0x3b5affff is written to the part. the value shifted out on the miso line while the fourth byte is sent is the value stored in the adc_ config _ high register. figure 93 . memory (mcr, bbram , or packet ram) block write figure 94 . memory (mcr, bbram , or packet ram) random address write figure 95 . memory (mcr, bbram , or packet ram) block read mosi miso spi_mem_wr ignore address sta tus dat a for [address] sta tus dat a for [address + 1] sta tus dat a for [address + 2] sta tus dat a for [address + n] sta tus 08291-030 cs mosi miso spi_memr_wr ignore sta tus sta tus address 2 address 1 sta tus dat a for [address 2] dat a for [address 1] sta tus dat a for [address n] sta tus 08291-142 cs mosi miso ignore spi_mem_rd address spi_no p spi_no p spi_no p sta tus sta tus spi_no p max n = (256-initia l address) 08291-143 cs dat a from address dat a from address + 1 dat a from address + n
adf7023 data sheet rev. c | page 60 of 112 figure 96 . memory (mcr, bbram , or packet ram) random address read spi_memr_wr ignore sta tus sta tus dat a from address 1 dat a from address 2 dat a from address n dat a from address n ? 2 dat a from address n ?1 address 1 address 2 address 3 address 4 address n spi_no p spi_no p 08291-144 mosi miso cs
data sheet adf7023 rev. c | page 61 of 112 low power modes the adf7023 can be configured to operate in a broad range of energy sensitive applications where battery lifetime is critical. this includes support for applications where the adf7023 is required to operate in a fully autonomous mode or applications where the host processor controls the transceiver during low power mode operation. t hese low power modes are imple - mented using a hardware wake - up controller (wuc), a firmware timer , and the smart wake mode functionality of the on - chip communications processor. the h ardware wuc is a low power wake - up controller (wuc) that comprises a 16- bit wake - up timer with a programmable prescaler. the 32.768 khz rcosc or xosc provides the clock source for the timer. the firmware timer is a software timer residing on the adf7023 . the firmware timer is used to count the number of wuc timeouts and s o can be used to count the number of adf7023 wake -ups. the wuc and the firmware timer , therefore , provide a real - time clock capability. us ing the low power wuc and the firmware timer, the swm firmware allows the adf7023 to wake up autonomously from sleep w ithout intervention from the host processor. during this wake - up period , the adf7023 is controlled by the communications processor. this functionality allows carrier sense, packet sniffing , and packe t reception while the host processor is in sleep, thereby dramatically reducing overall system current consumption. the smart wake mode can then wake the host processor on an interrupt condition. an overview of the low power mode configuration is shown in figure 97, and the register settings that are used for the various low power modes are described in table 28 . table 28 . settings for low power modes low power mode memory address register name bit description deep sleep modes 0x30d 1 wuc _ config _ low wuc _ bbram _ en 0: bbram contents are not retained during phy_sleep . 1: bbram contents are retained during phy_sleep . wuc 0x30c 1 wuc _ config _ high wuc _ prescaler [2:0] s ets the pre scaler value of the wuc . wuc 0x30d 1 wuc _ config _ low wuc _ rcosc _ en enables the 32.768 khz rc osc . wuc 0x30d 1 wuc _ config _ low wuc_x osc32k_en enables the 32.768 khz external osc . wuc 0x30d 1 wuc _ config _ low wuc _ clksel sets the wuc clock source. 1: rc osc selected . 2 : xosc selected . wuc 0x30d 1 wuc _ config _ low wuc _ arm enable to ensure that the device wakes from the phy_sleep state on a wuc timeout . wuc 0x30e 2 , 0x30f wuc _ value _ high wuc _ value _ low wuc _ timer _ value [15:0] the wuc timer value. 32,768 1) ( 2 + = ler wuc_presca value wuc_timer_ ) interval(s wuc wuc 0x101 interrupt _ mask _1 wuc _ timeout enables the interrupt on a wuc timeout . firmware t imer 0x100 interrupt _ mask _0 interrupt _ num _ wakeups enabling this interrupt enables the firmware timer. interrupt is set when the number _ of wakeups count exceeds the threshold. firmware t imer 0x102, 0x103 number _ of _ wakeups _0 number _ of _ wakeups _1 number _ of _ wakeups [15:0] number of adf7023 wake - ups. firmware t imer 0x104, 0x105 number _ of _ wakeups _ irq _ threshold _0 number _ of _ wakeups _ irq _ threshold _1 number _ of _ wakeups _ irq_ threshold [15:0] threshold for the number of adf7023 wake - ups. when exceeded , the adf7023 exit s low power mode. swm 0x11a mode _ control swm _ en enables s mart w ake m ode . swm 0x11a mode _ control swm _rssi_ qual enables rssi pre qualification in smart wake mode .
adf7023 data sheet rev. c | page 62 of 112 low power mode memory address register name bit description swm 0x108 swm _rssi_ thresh swm_rssi_ thresh [7:0] rssi threshold for rssi pre qualification. rssi threshold (dbm) = swm _rssi_ thresh ? 107 . swm 0x107 parmtime _ divider parmtime _ divider [7:0] tick rate for the r x dwell timer. swm 0x106 rx _ dwell _ time rx _ dwell _ time [7:0] time that the adf7023 remains awake during swm. receive d well t ime = rx _ dwell _ time ivider parmtime_d 128 mhz6.5 swm 0x100 interrupt _ mask _0 interrupt _ swm _rssi_ det interrupt _ preamble _ detect interrupt _ sync _ detect interrupt _ address _ match various interrupts that can be used in swm . 1 it is necessary to write to the 0x30c and 0x30d registers in the following order : wuc_c onfig_ h igh (address 0x30c), directly followed by writing to wuc_c onfig_ l ow (address 0x30d) . 2 it is necessary to write to the 0x30e and 0x30f registers in the following order : wuc_value _h igh (address 0x30e), directly followed by writing to wuc_value _l ow (address 0x30f) .
data sheet adf7023 rev. c | page 63 of 112 figure 97 . low power mode operation set wuc_timeout interrupt phy_sleep bbram re t ained? wuc configured? increment number_of_ w akeups set interrupt_num_ w akeups number_of_ w akeups > threshold? swm enabled? (swm_en = 1) rssi qua l enabled? (swm_rssi_qual) measure rssi rssi > threshold (swm_rssi_thresh) rssi int enabled? (interrupt_ swm_rssi_det) preamble detected? sync word detected? crc correct? address ma tch? an y interrupt set? time in rx > rx_dwell_time? set interrupt_ swm_rssi_det set interrupt_ preamble_detect set interrupt_ sync_detect set interrupt_ address_m a tch w ait for host command w ait for host command w ait for host command w ait for host command w ait for host command set interrupt_ crc_correct interrupt (if enabled) adf7023 host no no no no no no no and rx_dwell_time exceeded no no no no no yes yes yes yes yes yes yes yes yes yes yes no yes yes yes yes yes yes smart w ake mode smart w ake mode (carrier sense on ly) wuc and rtc modes dee p sleep mode 1 dee p sleep mode 2 08291-145
adf7023 data sheet rev. c | page 64 of 112 example low power mo des deep sleep mode 2 deep sleep m ode 2 is suitable for applications w here the host processor control s the low power mode timing and the lowest possible adf7023 sleep current is required. in this low power mode , the adf7023 is in the phy_sleep state . the bbram contents are not retained. this low power mode is entered by issuing the cmd_hw_reset command fro m any radio state. to wake the part from the phy_sleep state , the cs pin should be set low. the initialization routine after a cmd_hw_reset command should be followed as detailed in the radio control section. deep sleep mode 1 deep sleep m ode 1 is suitable for a pplications where the host processor control s the low power mode timing and the adf7023 configuration is retained during the phy_sleep state . in this low power mode , the adf7023 is in the phy_sleep state with the bbram contents retained. before entering the phy_sleep state, set wuc _ bbram _ en ( address 0x30 d ) to 1 to ensure that the bbram is retained. this low power mode is entered by issuing the c md_phy_sleep command from either the phy_off or phy_on state. to exit the phy_sleep state , the cs pin can be set low. then, follow t he cs low initialization routine , as detailed in th e radio control section. wuc mode in this low power mode , the hardware wuc is used to wake the adf7023 from the phy_sleep state after a user - defined duration. at the end of this duration, the adf7023 can provide an i nterrupt to the host processor. while the adf7023 is in the phy_sleep state , the host processor can optionally be in a deep sleep state to save power. before issuing the cmd_ phy_sleep command, the host processor should configure the wuc and se t the firmware timer threshold to zero ( number _ of _ wa k e u p s _ irq _ threshold = 0 , address 0x104 and address 0x105 ). the wuc_bbram_en ( address 0x30 d) s hould be set to 1 to ensure that the bbram is retained. on issuing the cmd_phy_ sleep command, t he device goes to sleep for a period until the hardware timer times out. at this point, the device wakes up , and , if wuc _ timeout or interrupt _ num _ wakeups interrupts are enabled (address 0x100) , the device asserts the irq_gp3 pin . the operation of this low power mode is illustrated in figure 98 . wuc mode with firmware timer in this low power mode , the wuc is used to periodically wake the adf7023 from the phy_sleep state, and the firmware timer is used to count the number of wuc timeouts. the combination of the wuc and the firmware timer provide s a real - time clock (rtc) capability. t he host processor should set up the wuc and the firmware timer before entering the phy_sleep state . the wuc_bbram_en ( address 0x30 d) s hould be set to 1 to ensure that the bbram is retained. the wuc can be configured to time out at some standard time interval ( for example, 1 s ec , 60 s ec ). on issuing the cmd_phy_sleep command, the device enters the phy_sleep state for a period until the hardware timer times out. at this point, the device wakes up , incre ments the 16 - bit firmware timer ( number _ of _ wa k e u p s , address 0x102 and address 0x103 ) and , if wuc _timeout is enabled (address 0x101) , the device asserts the irq_gp3 pin. if the16 - bit firmware count is less than or equal to the user set threshold ( number _ of _ wakeups _ irq _ threshold , address 0x104 and address 0x105 ), the device returns to the phy_sleep state . with this method, the firmware count ( numbe r_ of _ wa k e u p s ) equates to a real time interval. w hen the fi rmware count exceeds the user - set threshold ( number _ of _ wa k e u p s _ irq _ threshold ), the adf7023 asserts the irq_gp3 pin , i f the interrupt _ num _ wakeups bit (address 0x100) is set , and enters the phy_off state . the operation of this low power mode is illustrated in figure 99. smart wake mode (carrier sense o nly) in this low power mode , the wuc, firmware timer , and sm art wake mode are used to implement periodic rssi measurements on a particular channel ( that is, carrier sense). to enable this mode , the wuc and firmware timer should be configured before entering the phy_sleep state . the wuc_bbram_en ( address 0x30 d) s hou ld be set to 1 to ensure that the bbram is retained . the rssi measurement is enabled by setting swm _ rssi _ qual = 1 and swm_en = 1 (address 0x11a). interrupt _ swm _ rssi _ det (address 0x100) should also be enabled. if the measured rssi value is below the user - defined threshold set in the swm _ rssi _ thresh register ( address 0x108), the device return s to the phy_sleep state . if the rssi measurement is greater than the swm _ rssi _ thresh value, the device sets the interrupt _s wm _ rssi _ det i nterrupt to alert the host proc essor and waits in the phy_on state for a host command. the operation of this low power mode is illustrated in figure 100 .
data sheet adf7023 rev. c | page 65 of 112 smart wake mode in this low power mode the wuc, firmware timer , and smart wake mode are employed to periodically listen for packets. to enable this mode , the wuc and firmware timer should be configured and smart wake mode ( s wm ) enabled ( swm _ en , address 0x11a ) before entering the phy_sleep state . the wuc_bbram_en ( address 0x30 d) s hould be set to 1 to ensure that the bbram is retained . rss i pre qualification can be optionally enabled ( swm _ rssi _ qual = 1 , address 0x11 a ). when rssi pre qualification is enabled , the adf7023 begin s searching for the preamble only if the rssi measurement is greater than the user - defined threshold. the adf7023 is in the phy_rx state for a duration deter - mined by the rx _ dwell _ time setting ( address 0x106). if the adf7023 detects the preamble during the receive dwell time , it search es for the sync word. if the sync word routine is detected , the adf7023 load s the received data to packet ram and check s for a crc and address match , if enabled. if any of the receive packet interrupts ha s been set , the adf7023 return s to the ph y_on state and wait s for a host command. if the adf7023 receive s preamble detection during the receive dwell time but the remainder of the received packet extends beyond the dwell time , the adf7023 extend s the dwell time until all of the packet is received or the packet is recognized as invalid ( for example, there is an incorrect sync word). this low power mode terminates when a valid packet interrupt is received. alternatively, this l ow power mode can be terminated via a firmware timer timeout. this can be useful if certain radio tasks ( for example, ir calibration) or processor tasks must be run periodically while in the low power mode. the operation of this low power mode is illustrated in figure 101 . exiting low p ower m ode as described in figure 97, the adf7023 wait s for a host command on any of the termination conditions of the low power mode . it is also possible to perform an asynchro nous exit from low power mode using the following procedure: 1. bring the cs pin of the spi low and wait until the miso output goes high. 2. issue a cmd_h w_reset command. the host processor should then follow the initialization procedure after a cmd_hw_reset command, as described in the initialization section.
adf7023 data sheet rev. c | page 66 of 112 low power mode timin g diagrams figure 98 . low power mode timing w hen u sing the wuc figure 99 . low power mode timing when using the wuc and the firmware t imer figure 100 . low power mode timing w hen using the wuc, firmware t imer , and swm with c arrier s ense figure 101 . low power mode timing when using the wuc, f irmware t imer , and swm hos t : s t art wuc hos t : cmd_phy_slee p phy_off or phy_on adf7023 opera tion interrupt wuc_timeout (if enabled) interrupt interrupt_num_ w akeups (if enabled and number_of_ w akeups_irq_threshold = 0) phy_sleep wuc timeout period phy_off 08291-146 increment firm w are timer increment firm w are timer firm w are timer > threshold hos t : cmd_phy_slee p hos t : s t art wuc phy_off or phy_on adf7023 opera tion interrupt_ num_ w akeups phy_sleep phy_sleep phy_sleep phy_off wuc timeout period wuc timeout period number_of_ w akeups_irq_threshold rea l time interna l 08291-147 hos t : cmd_phy_slee p hos t : s t art wuc phy_off or phy_on adf7023 opera tion interrupt_ swm_rssi_det phy_sleep rssi threshold rssi threshold rssi > threshold rssi rssi rssi phy_sleep phy_sleep phy_on wuc timeout period wuc timeout period 08291-148 08291-149 hos t : cmd_phy_slee p hos t : s t art wuc phy_off or phy_on adf7023 opera tion interrupt_ swm_rssi_det interrupt_ preamble_detect interrupt_ sync_detect interrupt_ crc_correct interrupt_ address_m a tch phy_sleep no p acket detected no p acket detected p acket detected rx rx phy_sleep phy_sleep phy_on wuc timeout period wuc timeout period init phy_rx receive dwel l time (rx_dwell_time)
data sheet adf7023 rev. c | page 67 of 112 wuc setup circuit description the adf7023 features a low power wake - up controller comprising a 16- bit wake - up timer with a 3- bit programmable pre scaler , as illustrated in figure 102. the pre scaler clock source can be con figured to use either the 32.76 khz internal rc oscillator (rcosc) or the 32.76 khz external oscillator (xosc). this combination of programmable prescaler and 16 - bit down counter gives a total hardware timer range of 30.52 s to 36.4 hours. configuration and operation the hardware wuc is configured via the following registers: ? wuc _ config _ high ( address 0x30 c) ? wuc _c onfig _l ow ( address 0x30 d) ? wuc _v alue _ high ( address 0x30e) ? wuc _v alue _ low ( address 0x30f ) the relevant fields of each register are detailed in table 29 . all four of these registers are write only. the wuc should be configured as follows : 1. clear all interrupts . 2. set required interrupts . 3. write to wuc _ config _ high and wuc _ config _ low . ensure that wuc _ arm =1. ensure that wuc _ config _ bbram _ en =1 (retain bbram during phy_sleep). i t is necessary to write to both registers together in the following order: wuc _c onfig _h igh directly followed by writing to wuc _c onfig _l ow . 4. write to wuc _v alue _ high and wuc _v alue _ low . this configures the wuc _ timer_ va lu e [15:0] and , thus , the wuc timeout period. the timer begin s counting from the configured value after these registers ha ve been written to. it is necessary to write to both registers together in the following order : wuc _ tiimer_ va lu e _h igh directly followed by writing to wuc _ va lu e _ low . figure 102 . hardware wake - up controller (wuc) adf7023 w ake-u p circuit 16-bit down counter 16-bit reload v alue prescaler 32.768khz tick r a te 1 0 rc oscill at or 32khz x tal wuc wuc_config_low[4] wuc_ v alue_high wuc_ v alue_low t o firm w are timer wuc_config_high[2:0] wuc_timeout interrupt 08291-150
adf7023 data sheet rev. c | page 68 of 112 table 29. wuc r egister s ettings wuc setting name description wuc_value_high [7:0] wuc _ timer_ value [15:8] wuc timer value . 32,768 1) ( 2 + = ler wuc_presca value wuc_timer_ )interval(s wuc wuc_value_low [7:0] wuc _ timer_ value [7:0] wuc timer value . wuc _ config _ high [7] r eserved set to 0 . wuc_config_high[6:3] rcosc_coarse_cal_value rcosc_coarse_cal_value change in rc oscillator frequency coarse tune state 0000 +83% state 10 0001 +66% state 9 1000 +50% state 8 1001 +33% state 7 1100 +16% state 6 1101 0% state 5 1110 ?16% state 4 1111 ?33% state 3 0110 ?50% state 2 0111 ?66% state 1 wuc_config_high[2:0] wuc_prescaler wuc_prescaler 32.768 khz divider tick period 000 1 30.52 s 001 4 122.1 s 010 8 244.1 s 011 16 488.3 s 100 128 3.91 ms 101 1024 31.25 ms 110 8192 250 ms 111 65,536 2000 ms wuc_config_low [7] reserved set to 0. wuc_config_low [6] wuc_rcosc_en 1: enable. 0: disable rcosc32k. wuc_config_low [5] wuc_xosc32k_en 1: enable. 0: disable xosc32k. wuc_config_low [4] wuc_clksel 1: rc 32.768 khz oscillator. 0: external crystal oscillator. wuc_config_low [3] wuc_bbram_en 1: enable power to bbram during the phy_sleep state. 0: disable power to bbram during the phy_sleep state. wuc_config_low [2:1] reserved set to 0. wuc_config_low [0] wuc_arm 1: enable wake - up on wuc timeout event. 0: disable wake - up on wuc timeout event.
data sheet adf7023 rev. c | page 69 of 112 firmware timer setup the adf7023 wake s up from the phy_sleep state at the rate set by the wuc. a firmware timer, implemented by the on - chip processor, can be used to count the number of hard ware wake - ups and generat e an interrupt to the host processor . thus , the adf7023 can be used to handle the wake - up timing of the host processor, reducing overall system power consumption. to set up the firmware timer, the host processor must set a value in the number _ of _ wa k e u p s _ irq _ threshold [15:0] registers ( address 0x104 and address 0x105) . this 16 - bit value represents the number of times the device wake s up before it interrupts the host processor. at each wake - up, the adf7023 increment s the number _ of _ wakeups [15:0] reg is ter (address 0x103) . if this value exceeds the value set by the number _ of _ wa k e u p s _ irq _ threshold [15:0] register, the number _ of _ wakeups [15:0] value is cleared to 0. at this time, if the interrupt _ num _ wakeups bit in the interrupt _ mask _0 register ( address 0x100 ) is set, the device assert s the irq_gp3 pin and enter s the phy_off state. calibrating the rc o scillator there are two types of rc oscillator calibration, fine and coarse calibrations. a fine calibration of the rc oscillator is automatically performed upon wake up from phy_sleep and upon cold start. the user can a lso manually initiate a fine calibration. to meet the quoted rc oscillator frequency accuracy given in the s pecifications section , it is necessary to perform a coarse calibration of the rc oscillator. performing a fine calibration of the rc oscillator this is performed as follows: 1. write to the wuc_config_hig h and wuc_config_low registers, setting the wuc_ rcosc_en bit high. 2. write a 0 to wuc_rcosc_cal_en in the wuc_flag_reset register. 3. write a 1 to wuc_rcosc_cal_en in the wuc_flag_reset register. during calibration, the host microprocessor can write to and read from memory locations and issue commands to the adf7023. the rc oscillator calibration status can be viewed in the wuc_status register (location 0x311). the result of a fine calibration can be read back from the rcosc_cal_readback_ high (location 0x34f) an d rcosc_cal_readback_low (location 0x350) registers. a fine calibration typically takes 1.5 ms. performing a coarse calibration of the rc oscillator this calibration involves performing fine calibrations of the rc oscillator for different values of rcosc_coarse_cal_value to determine the optimum value to be written to wuc_config_high (location 0x30c[6:3]). the coarse calibration procedure is outlined in figure 103. typically, the optimum coarse tune state is state 5 , and the algorithm starts in this state to minimize the number of iterations. usually, the optimum rcosc_coarse_cal_value is determined at 25c once , and the result stored in the host microprocessor. this result can be incorporated in the value written to wuc_config_high prior to fine calibrations of the rc oscillator.
adf7023 data sheet rev. c | page 70 of 112 figure 103 . rc oscillator coarse calibration algorithm set i = 5 set coarse cal state = i initiate fine cal and wait 1.25ms readback fine cal result (i) and calculate fine_cal_code_delta(i) = fine_cal_code(i) ? 300 increment i set coarse cal state = i is fine_cal_code_delta(i) positive? yes no decrement i set coarse cal state = i initiate fine cal and wait 1.25ms initiate fine cal and wait 1.25ms readback fine cal result (i) and calculate fine_cal_code_delta(i) = fine_cal_code(i) ? 300 readback fine cal result (i) and calculate fine_cal_code_delta(i) = fine_cal_code(i) ? 300 is abs(fine_cal_code_delta(i)) < abs(fine_cal_code_delta(i+1))? is abs(fine_cal_code_delta(i)) < abs(fine_cal_code_delta(i?1))? yes yes no no exit optimum coarse cal state = i+1 exit optimum coarse cal state = i?1 is i = 1? no exit optimum coarse cal state = 1 yes is i = 10? no exit optimum coarse cal state = 10 yes 08291-103
data sheet adf7023 rev. c | page 71 of 112 downloadable firmwar e modules the program ram memory of the adf7023 can be used to store firmware modules for the communications processor that provide the adf7023 with extra functionality. the binary code for these firmware modules and detail on their functionality are available from analog devices . three m odules are briefly described in this section , namely, image rejection calibration, aes encryption and decryption , a nd reed solomon coding . writing a module to program ram the sequence to write a firmware module to program ram is as follows: 1. ensure that the adf7023 is in phy_off . 2. issue the cmd_ram_load_init command. 3. write the module to program ram using an spi memory bl ock write ( see the spi interface section) . 4. issue the cmd_ram_load_done command . the firmware module is now stored on program ram . image rejection cal ibration module the calibration system initially disables the adf702 3 receiver, and an internal rf source is applied to the rf input at the image frequency. the algorithm then maximizes the receiver image rejection performance by iteratively minimizing the quadrature gain and phase errors in the polyphase filter. the calib ration algorithm takes its initial estimates for quadra - ture phase correction ( address 0x118 ) and quadrature gain correction ( address 0x11 9 ) from bbram. after calibration, new optimum values of phase and gain are loaded back into these locations. these cal ibration values are maintained in bbram during sleep mode and are automatically reapplied from a wake - up event, which keeps the number of calibrations required to a minimum. depending on the initial values of quadrature gain and phase correction, the calibration algorithm can take approximately 20 ms to find the optimum image rejection performance. however, the calibration time can be significantly less than this when the seed values used for gain and phase correction are close to optimum. the image rejection performance is also dependent on tempera ture. to maintain optimum image rejection perform ance, a calibration should be activated whenever a temperature change of more than 10c occurs. the adf702 3 on - chip temperature sensor can be used to determine whe n the temperature exceeds this limit. reed solomon coding module this coding module uses reed solomon block coding to detect and correct errors in the received packet. a transmit message of k bytes in length, is appended with an error check ing code (ecc ) of length n ? k bytes to give a total message length of n bytes, as shown in figure 104 . figure 104 . packet s tructure with a ppended reed solomon error c heck c ode (ecc) the receiver decodes the ecc to detect and correct up to t bytes in error, where t = (n ? k)/2. the firmware supports correction of up to five bytes in the n byte field. to correct t bytes in error , an ecc length of 2t bytes is required , and the byte errors can be randomly distributed throughout the payload and ecc fields. reed solomon coding exhibits excellent burst error correction capability and is commonly used to improve the robustness of a radio link in the presenc e of transient interference or due to rapid signal fading conditions that can corrupt sections of the message payload. reed solomon coding is also capable of improving the receivers sensitivity performance by several db, where random errors tend to dominate under low snr conditions and the receivers packet error rate performance is limited by thermal noise. the number of consecutive bit errors that can be 100% corrected is {(t ? 1) 8 + 1}. longer, random bit - error patterns, up to t bytes, can also be corrected if the error patterns start and end at byte boundaries. the firmware also takes advantage of an on - chip hardware accelerator module to enhance throughput and minimize the latency of the reed solomon processing . aes encryption and d ecryption module the downloadable a es firmware module supports 128 - bit block encryption and decryption with key sizes of 128 bits , 192 bits , and 256 bits. two modes a re supported: ecb mode and cbc mode 1. ecb mode si mply encrypts/decrypts on a 128- bit block by block with a single secret key as illustrated in figure 105 . cbc m ode 1 encrypts after first adding (m odulo 2) , a 128 - bit user supplied initialization vector. the resulting cipher text is then used as the initialization vector for the next block and so forth , as illustrated in figure 106 . decryption provides the inverse function ality. the firmware also takes advantage of an on - chip hardware accelerator module to enhance throughput and minimize the latency of the aes processing . 08291-151 n bytes k bytes (n ? k) bytes preamble sync word pa yload ecc
adf7023 data sheet rev. c | page 72 of 112 figure 105 . ecb mode. figure 106 . cbc mode 1 128 bits 128 bits aes enc rypt ke y 128 bits 128 bits aes enc rypt ke y 128 bits 128 bits aes enc rypt ke y plain text cypher text ecb mode 08291-152 initia l vec t or plain text cypher text cbc m o de 1 08291-153 128 bits 128 bits aes enc rypt ke y + 128 bits 128 bits aes enc rypt ke y + 128 bits 128 bits aes enc rypt ke y + 128 bits 128 bits aes enc rypt ke y +
data sheet adf7023 rev. c | page 73 of 112 radio blocks f requency synthesizer a fully integrated rf frequency synthesizer is used to generate both the transmit signal and the receive rs local oscillator (lo) signal. the architecture of the frequency synthesizer is shown i n figure 107. the receiver uses a f ractional - n frequen cy synthesizer to gene rate the m ixers lo for down conversion to the intermediate frequency (if) of 200 khz or 30 0 khz. in transmit mode, a high resolution sigma- delta ( - ) modulator is used to generate the required frequency deviations at the rf output when fsk data is transm itted. to reduce the occupied fsk bandwidth, the transmitted bit stream can be filtered using a digital gaussian filter, which is enabled via the radio _ cfg _9 register ( address 0x115). the gaussian filter uses a bandwidth time ( bt ) of 0.5. the vco and the pll loop filter of the adf702 3 are fully integrated. to reduce the effect of pulling of the vco by the power - up of the pa and to minimize spurious emissions, the vco operates at twice or four times the rf frequency. the vco signal is then d ivided by 2 or 4, giving the requ ired frequency for the transmit ter and the required lo frequency for the receiver. a high speed, fully automatic calibration scheme is used to ensure that the frequency and amplitude characteristic of the vco are maintained over temperature, supply voltage, and process variations. the calibra tion is automatically performed when the cmd_phy_rx or cmd_phy_tx command is issued. the calibra tion duration is 142 s, and i f required, the calibration _ status register ( address 0x339) can be polled to indicate the completion of the vco self -calibration. after the vco is calibrated, the fre quency synthe sizer settle s to within 5 ppm of the target frequency in 56 s. figure 107 . rf f requency synthesizer a rchitecture synthesizer bandwidth the synthesizer loop filter is fully integrated on chip and has a programmable bandwidth. the communications processor automatically sets the bandwidth of the synthesizer when the device enters phy_tx or phy_rx state . on e ntering the phy_tx state, the communications processor chooses the bandwidth based on the pr ogrammed modulation scheme (2 fsk, gfsk , or ook) and the data rate. this ensures optimum modulation quality for each data rate. on entering the phy_rx state, the com munications processor sets a narrow bandwidth to ensure best receiver rejection. in all , there are eight bandwidth configurations. each synthesizer bandwidth setting is described in table 30. table 30 . automatic s ynthesizer bandwidth s elections description data r ate (kbps) closed loop s ynthesizer b andwidth (khz) rx 2fsk/gfsk /msk/gmsk all 92 tx 2fsk/gfsk/msk/gmsk 1 to 49. 5 130 tx 2fsk/gfsk/ msk/gmsk 49. 6 to 99. 1 174 tx 2fsk/gfsk/ msk/gmsk 99. 2 to 129. 5 174 tx 2fsk/gfsk /msk/gmsk 129. 6 to 179. 1 226 tx 2fsk/gfsk /msk/gmsk 179. 2 to 2 39.9 305 tx 2fsk/gfsk /msk/gmsk 240 to 300 382 tx ook all 185 synthesizer settling after the vco calibration, a 56 s delay is allowed for synthesizer settling. this delay is fixed at 56 s by default and ensures that the synthesizer has fully settled when using any of the default synthesizer bandwidths. however , in some cases , it may be necessary to use a custom synthesizer settling delay. to use a custom delay , set the custom _ trx _ synth _ lock _ time en bit to 1 in the mode_control register (address 0x11a) . the synthesizer settling delays for the phy_rx and phy_tx state transitions can be set independently in rx _ synth _ lock _ time register ( address 0x13e) and the tx _ synth _ lock _ time register ( address 0x13f). the settling time can be set in the range 2 s to 512 s in steps of 2 s. bypassing vco calibration it is possible to bypas s the vco calibration for ultra fast frequency hopping in transmit or receive. the calibration data for each rf channel sh ould be stored in the host processor memory. th e calibration data comprises two values: the vco band select value and the vco amplitude level. read and store calibration data 1. go to the phy_tx or phy_rx state without bypassing the vco calibration. 2. read the following mcr registers and store the calibrated data in memory on the host processor: a. vco _ band _ readback ( address 0x3da) b. vco _ ampl _ readback ( address 0x3db) f_deviation rf freq loop filter vco 26mhz ref tx data frac-n integer-n n divider vco calibration - divider gaussian filter pfd charge pump 2 or 4 2 08291-035
adf7023 data sheet rev. c | page 74 of 112 bypassing vco calibration on cmd_phy_tx or cmd_phy_rx 1. ensure that the bbram is configured . 2. set vco _ ovrw _ en (address 0x3cd) = 0x3 . 3. set vco _ cal _ cfg (address 0x3d0) = 0x0f . 4. set vco _ band _ ovrw _ va l (address 0x3cb) = stored vco _ band _ readback (address 0x3da) for that channel . 5. set vco _ ampl _ ovrw _ va l (address 0x3cc) = stored vco _ ampl _ readback (address 0x3db) for that channel . 6. set synth _ cal _ en = 0 (in the calibration _ control register , address 0x338) . 7. set synth _ cal _ en = 1 (in the calibration _ control register, address 0x338 ). 8. issue cmd_phy_tx or cmd_phy_rx to go to the phy_tx or phy_rx state without the vco calibration . crystal oscillator a 26 mhz crystal oscillator operating in parallel mode must be connected between the xosc26p and xosc26n pins. two parallel loading capacitors are required for oscillation at the correct frequency. their values are dependent upon the crystal specification. they should be chosen to ensure that the shunt value of capacitance added to the pcb track capacitance and the input pin capacitanc e of the adf7023 equals the specified load capacitance of the crystal, usually 10 pf to 20 pf. track capacitance values vary from 2 pf to 5 pf, depend ing on board layout. the total l oad capacitance is described by c load = pcb c pin c 2 c 1 c ++ + 2 11 1 w here : c load is the total load capacitance . c1 and c2 are the external crystal load capacitors . c pin is the adf7023 input capacitance of the xosc26p and xosc26n pins and is equal to 2.1pf . c pcb is the pcb track capacitance. when possible, choose capacitors that have a very low temperature coefficient to ensure stable frequency operation over all conditions. the crystal frequency error can be corrected by means of an integrated digital tuning varactor. for a typical crystal load capacitance of 10 pf, a tuning ran ge of + 15 ppm to ? 11.25 ppm is available via programming of a 3 - bit dac, according to table 31. the 3 - bit value should be written to xosc_cap_dac in the osc_config register (address 0x3d2). alternatively, any error in the rf frequency due to crystal error can be adjusted for by offsetting the rf channel frequency using the rf channel frequency setting in bbram memory . table 31 . crystal frequency pulling programming xosc_cap_dac pulling (ppm) 000 + 15 001 + 11.25 010 + 7.5 011 + 3.75 100 0 101 ? 3.75 110 ? 7.5 111 ? 11.25 modulation the adf7023 supports binary frequency shift keying ( 2 fsk), minimum shift keying (msk), binary level gaussian filtered 2 fsk (gfsk), gaussian filtered msk (gmsk) , and o n-o ff k eying (ook). the desired transmit and receive modulation formats are set in the radio _ cfg _9 register ( address 0x115). when using 2fsk/g fsk/msk/gmsk modulation , t he frequency deviation can be set using the freq _ deviation [11:0] parameter in the radio _ cfg _1 register ( address 0x10d) and radio _ cfg _1 register ( address 0x10e). the data rate can be set in the 1 kbps to 300 kbps range using the data _ rate [11:0] parameter in the radio _ cfg _0 register ( address 0x10c) and radio _ cfg _1 register ( address 0x10d). for gfsk/gmsk modulation , the gaussian filter uses a fixed bandwidth time (bt) product of 0.5. when using ook modulation , it is recommended to enable manchester encoding (manchester_enc = 1, address 0 x11c). the data rate can be set in the 2.4 kbps to 19.2 kbps range (4.8 kcps to 38.4 kcps manchester encoded) using the data_rate[11:0] parameter in the radio_cfg_0 register (ad dress 0x10c) and radio_cfg_1 register (address 0x10d). rf output stage power amplifier (pa) the adf702 3 pa can be configured for single- ended or differential output operation using the pa _ single _ diff _ sel bit in the radio _ cfg _8 register (address 0x114). the pa level is set by the pa _ level bit in the radio _ cfg _8 register and has a range of 0 to 15. for finer control of the output power leve l, the pa _ level _ mcr register (address 0 x307) can be used . i t offers more resolution with a setting range of 0 to 63. t he relationship between the pa_level and pa_level _ mcr settings is given by pa_level_mcr = 4 pa _l evel + 3 the single - ended config uration can deliver 13.5 dbm output power. th e differential pa can deliver 1 0 dbm output power and allows a straightforward interface to dipole antenna e. the two pa configurations offer a tx antenna diversity capability. note that the t wo pas cann ot b e enabled at the same time.
data sheet adf7023 rev. c | page 75 of 112 automatic pa ramp the adf702 3 has built - in up and down pa ramping for both single- ended and differe ntial pas. there are eight ramp rate settings, with the ramp rate defined as a certain number of pa power level settings per data bit period. t he pa _r amp variable in the radio _ cfg _8 register (address 0x1 14 ) sets this pa ramp rate, as illustrated in figure 108 . figure 108 . pa r amp for d ifferent pa_ramp s ettings the pa ramps to the level set by the pa _ level or pa _ level _ mcr settings. en abling the pa ramp reduces spectral splatter and helps meet radio regulations (for example, the etsi en 300 220 standard) , which limit pa transient spurious emissions . to ensure optimum performance , an adequately long pa ramp rate is required based on the data rate and the pa output power setting . the pa _ ramp setting should, therefore , be set such that ramp rate ( codes / bit ) 10,000 ][ ][ 11:0 data_rate 5:0 cr pa_level_m where pa_level_mcr is related to the pa_level setting by pa_level_mcr = 4 pa_level + 3. pa/lna inte rface the adf7023 supports both single - ended and differential pa outputs. only one pa can be active at one time. the differential pa and lna share the same pins, rfio_1p and rfio_1n, which facilitate a simpler antenna interface. the single - ended pa output is available on the rfo2 pin. a number of pa/lna antenna matching options are possible and are described in the pa/lna section. receive channel filt er the receivers channel filter is a fourth order, active poly phase butterworth filter w ith programmable bandwidths of 100 khz, 150 khz, 200 khz , and 300 khz. the fourth order filter gives very good interference suppression of adjacent and neigh - boring chann els and also suppresses the image channel by approximately 3 6 db at a 100 khz if bandwidth and an rf f requency of 868 mhz or 915 mhz . for channel bandwidths of 100 khz to 200 khz , an if frequency of 200 khz is used , which results in an image frequency loc ated 400 khz below the wanted rf frequency. when the 300 khz bandwidth is selected , an if frequency of 300 khz is used , and the image frequency is located at 600 khz below the wanted frequency. the bandwidth and center frequency of the if filter are calibr ated automatically after entering the phy_on state if the bb_cal bit is set in the mode_control register (address 0x11a). the filter calibration time takes 100 s. the if bandwidth is programmed by setting the ifbw field in the radio_cfg_9 register (addre ss 0x115). the filters pass band is centered at an if frequency of 200 khz when bandwidths of 100 khz to 20 0 khz are used and centered at 300 khz when an if bandwidth of 300 khz is used. image channel reject ion the adf7023 is capable of providing improved receiver image rejection performance by the use of a fully integrated image rejection calibration system under the control of the on - chip communications processor. to operate the calibration system, a firmware m odule is downloaded to the on - chip program ram. the firmware download is supplied by analog devices and described in the downloadable firmware modules section. to achieve the typical uncalibrated image attenuation values given in the specifications section , it is required to use recommended default values for image_reject_cal_phase (address 0x118) and image_reject_cal_amplitude (address 0x119). to achieve the specified uncalibrated image attenuation at 433 mhz, set image_reject_cal_ampl itude = 0 x03 and image_reject_cal_phase = 0x08 . to achieve the specified uncalibrated image attenuation at 868 mhz/915 mhz, set image_reject_cal_amplitude = 0x07 and image_reject_cal_phase = 0x16 . automatic gain contr ol (agc) agc is enabled by default, and keeps the receiver gain at the correct level by selecting the lna, mixer , and filter gain settings based on the measured rssi level. the lna has three gain levels , the m ixer has gain two levels, and the f ilter has three gain levels. in all , there are s ix agc stages , which are defined in table 32. table 32 . agc gain modes gain mode lna g ain mixer gain filter gain 1 high high high 2 high low high 3 medium low high 4 low low high 5 low low medium 6 low low low data bits pa ramp 0 (no ramp) pa ramp 1 (256 codes per bit) pa ramp 2 (128 codes per bit) pa ramp 3 (64 codes per bit) pa ramp 4 (32 codes per bit) pa ramp 5 (16 codes per bit) pa ramp 6 (8 codes per bit) pa ramp 7 (4 codes per bit) 1 2 3 4 ... 8 ... 16 08291-036
adf7023 data sheet rev. c | page 76 of 112 the agc remains at each gain stage for a time defined by the agc _ clk _ divide register ( address 0x32f). the default value of agc_clk_divide = 0x28 gives an agc delay of 25 s. when the rssi is above agc_high_threshold (address 0x35f) , the gain is reduced. when the rssi is below agc_low_ threshold (address 0x35e), the gain is increased. the agc can be configured to remain active while in the phy_rx state or can be locked on prea mble detection. the agc can also be set to manual mode , in which case the host processor must set the lna, filter , and mixer gains by writing to the agc _ mode register ( address 0x35d). the agc operation is set by the agc _ lock_mode setting in the radio _ cfg _7 register (address 0x113) and is described in table 33 . the lna, filter and mixer gains can be read back through the agc _ gain _ status register ( address 0x360). t able 33 . agc operation agc _ lock_mode bits in radio_cfg_ 7 register description 0 agc is free running . 1 agc is disabled. gains must be set manually . 2 agc is held at the current gain level . 3 agc is locked on preamble detection . rssi the rssi is based on a successive compression, log - amp architecture following the analog channel filter. the analog rssi level is digitized by an 8 - bit sar adc for user readback and for use by the digital agc controller. the adf7023 has a total of f our rssi measurement functions that support a wide range of applications. these functions can be used to implement carrier sense (cs) or clear channel assessment (cca). in packet mode , the rssi is automatically recorded in mcr memory and is available for user readback after rece i pt of a packet. table 36 details the four rssi measurement me thods. rssi method 1 w hen a valid packet is received in packet mode , the rssi lev el during postamble is automatically loaded to the rssi _ readback register ( address 0x312) b y the communications processor. the rssi _ readback register contains a two s complement value and can be converted to input power in dbm using rssi(dbm) = rssi_readback ? 107 to extend the linear range of rssi measurement down to an input power of ? 110 dbm (see figure 69 ), a cosine adjustment can be applied using the foll owing formula: rssi(dbm) = cos ? ? ? ? ? ? ? ? readback rssi _ 8 rssi_readback ? 106 w here cos(x) is the cosine of a ngle x (radians). rssi method 2 the cmd_get_rssi command can be used from the phy_on state to read the rssi. this rssi measurem ent method uses additional low pass filtering , resulting in a more accurate rssi reading. the rssi result is loaded to the rssi _ readback register (address 0x312) by the communications processor . the rssi_readback register contains a twos complement value and can be conver ted to input power in dbm using the following formula: rssi(dbm) = rssi_readback ? 107 rssi method 3 this method supports the measurement of rssi by the host processor at any time while in the phy_rx state . the receiver input power can be calculated using the following procedure: 1. set agc to hold by setting the agc_mode register ( address 0x35d ) = 0x40 (only necessary if agc has not been locked on the preamble or sync word ). 2. read back the agc gain settings ( agc _ gain _ status register, address 0x360) . 3. read the adc_readback [7:0] value ( address 0x327 and address 0x328; see the a nalog - to - digital converter section) . 4. re - enable the agc by setting the agc_mode r egister (address 0x35d ) = 0x00 (o nly necessary if agc has not already been locked on the preamble or sync word ). 5. calculate the rssi in dbm as follows: rssi(dbm) = 109 _ 7 1 _ ? ? ? ? ? ? ? + correction gain :0] readback[7 adc where gain_c orrection is determined by the value of the agc _ gain _ status register ( address 0x360) as shown in table 34. table 34 . gain mode correction for 2fsk/gfsk/msk/gmsk rssi agc_gain_status (a ddress 0x360) gain_correc tion 0x00 44 0x01 35 0x02 26 0x0a 17 0x12 10 0x16 0 to simplify the rssi calculation, the following approximation can be used by the host processor : 7 1 8 1 ? ? ? ? ? ? ++ 64 1 8 1 1
data sheet adf7023 rev. c | page 77 of 112 rssi method 4 this method is used to provide rssi readback when using ook demodulation in the phy_rx state. the receiver input power can be calculated using the following procedure: 1. set agc to hold by setting the agc_mode register (address 0x35d) = 0x40 (only necessary if agc has not been locked on the preamble or sync word ). 2. read back the agc gain settings (agc_gain_status register, address 0x360). 3. read the agc_ adc_word [6:0] value ( address 0x3 61 ). 4. re- enable the agc by setting the agc_mode register (address 0x35d) = 0x00 (only necessary if agc has not already been locked on the preamble or sync word ). 5. calculate the rssi in dbm as follows: rssi(dbm) = (agc_adc_word[6:0] 7 2 + gain_ correction) ? 110 w here gain_c orrection is determined by the value of the agc_gain_ status register (address 0x360) as shown in table 35. table 35 . gain mode correction for ook rssi agc_gain_status (a ddress 0x360) gain_correction 0x00 47 0x01 37 0x02 28 0x0a 19 0x12 10 0x16 0 to simplify the rssi calculation, the following approximation can be used by the host processor : ? ? ? ? ? ? ++ 64 1 8 1 1 8 2 7 2 table 36 . summary of rssi measurement methods rssi method rssi type modulation available in packet mode available in sport mode description 1 automatic end of packet rssi 2fsk/gfsk/ msk/gmsk y es no automatic rssi measurement du ring reception of the postamble in packet m ode. the rssi result is available in the rssi_readback register (address 0x312). 2 cmd_get_rssi command from phy_on 2fsk/gfsk/ msk/gmsk y es y es automatic rssi measurement from phy_on using cmd_get_rssi. the rssi result is available in the rssi_readback register (address 0x312). 3 rssi via adc and agc readback, fsk 2fsk/gfsk/ msk/gmsk y es y es rssi measurement based on the adc and agc gain readbacks. the h ost processor calculates rssi in dbm. 4 rssi via adc and agc r eadback, ook ook y es y es rssi measurement based on the adc and agc gain readbacks. the h ost processor calculates rssi in dbm.
adf7023 data sheet rev. c | page 78 of 112 2 fsk/gfsk/msk/gmsk de modulation a correlator demodulator is used for 2 fsk, gfsk, msk , and gmsk demodulation. the quadrature outputs of the if filter are first limited and then fed to a digital frequency correlator that performs filtering and frequency discrimination of the 2fsk/gfsk/msk/gmsk spectrum. d ata is recovered by comparing the outp ut levels from two correlators. the performance of this frequency discriminator approximates that of a matched filter detector, which is known to provide optimum detection in the presence of additive white gaussian noise (awgn). this method of 2fsk/gfsk/msk/gmsk demodulation provides approximately 3 db to 4 db better sensitivity than a linear frequency discriminator. the 2fsk/gfsk/msk/gmsk demodulator architecture is shown in figure 109 . the adf7023 is configured for 2fsk/gfsk/msk/ gmsk demodulation by setting demod _ scheme = 0 in the radio _ cfg _9 register (address 0x115). to optimize receiver sensitivity, the correlator bandw idth and phase must be optimized for the specific deviation frequency, data rate , and maximum expected frequency error between the transmitter and receiver. the bandwidth and phase of the discriminator must be set using the discrim _ bw bit in the radio _ cfg _3 register (address 0x10f) and the discrim _ phase [1:0] bit in the radio _ cfg _ 6 register (address 0x112). the discriminator setup is performed in three steps . step 1: calculate the d iscriminator bandwidth c oefficient k the d iscriminator bandwidth c oefficient k depends on the modulation index (mi) , which is determined by datarate dev fsk mi _2 = w here fsk_dev is the 2fsk/gfsk/msk/gmsk frequency deviation in hertz (hz) , measured from the carrier to the +1 symbol frequency (positive frequency deviation) or to the ? 1 symbol frequency (negative frequency deviation) , and d atarate is the data rate in bits per second ( bps ). the value of k is then determined by mi 1, afc off: k = floor ? ? ? ? ? ? dev fsk freq if _ _ mi < 1, afc off: k = floor ? ? ? ? ? ? ? ? ? ? 2 _ datarate freq if mi 1, afc on: k = floor ? ? ? ? ? ? + max error freqdev fsk freq if __ _ _ mi < 1, afc on: k = floor ? ? ? ? ? ? ? ? ? ? + max error freq datarate freq if __ 2 _ w here : mi is the modulation index. k is the discriminator coeff icient. floor[] is a function to ro und down to the nearest integer. if_f req is the if frequency in hertz (200 khz or 300 khz) . fsk_ de v is the 2fsk/gfsk/msk/gmsk frequency deviation in h ertz. freq_error_m ax is the maximum expected frequency error, in hertz , between tx and rx. step 2: calculate the discrim _ bw setting the bandwidth setting of the discrimi na tor is calculated based on the d iscriminator c oefficient k and the if frequency. the bandwidth is set using the discrim _ bw setting ( address 0x10f) , which is calculated accordin g to discrim_bw [7:0] = round ? ? ? ? ? ? freq if mhz k _ 25.3 step 3: calculate the discrim _ phase s etting the phase setting of the discrimina tor is calculated based on the d iscriminator c oefficient k , as described in table 37 . the phase is set using t he discrim _ phase [1:0] value in the radio _ cfg _6 register (address 0x112). table 37 . setting the discrim _ phase[1:0] v alue b ased on k k k/2 (k + 1)/2 discrim _ phase [1:0] e ven o dd 0 o dd e ven 1 even even 2 odd odd 3
data sheet adf7023 rev. c | page 79 of 112 figure 109 . 2 fsk/gfsk /msk/gmsk demodulation and afc architecture afc the adf7023 features a n internal real - time automatic frequency control loop. in receive, the control loop automatically monitors the frequency error during the packet preamble sequence and adjusts the receiver synthesizer local oscillator using proportional integral (pi) control. the afc frequency error measurement bandwidth is targeted specifica lly at th e packet preamble sequence ( dc f ree). afc is supported during 2fsk/gfsk/msk/gmsk de modulation. afc can be configured to lock on detection of the qualified preamble or on detection of the qualified sync word. to lock afc on detection of the qualifi ed preamble , set afc_lock_mode = 3 ( address 0x116 ) and ensur e that preamble detection is enabled in the preamble_match register (address 0x 11b ). afc lock is released if the sync word is not detected immediately after the end of the preamble. i n p acket mode, if the qualified preamble is followed by a qualified sync word, the afc lock is maintained for the duration of the packet . in s port mode , the afc lock is released on transitioning back to the phy_on state or when a cmd_phy_rx is issued while in the phy_rx state . to lock afc on detection of the qualified sync word , set afc_lock_mode = 3 and ensure that preamble detection is disabled in the preamble_match register (address 0x11b). if this mode is selected , consideration must be given to the selec tion of the sync word. the sync word should be dc free and have short run lengths yet low correlation with the preamble sequence. see the sync word description in the packet mode section for further details. after lock on detection of the qualified sync word , t he afc lock is maintained for the duration of the packet. in sport mode, the afc lock is released on transitioning back to the phy_on state or when cmd_ phy_rx is issued while in the phy_rx state. afc is enabled by setting afc _ lock _ mode in the radio _ cfg _10 register (address 0x116) , as described in table 38. table 38 . afc m ode afc _ lock _ mode [1:0] mode 0 free r unning: afc is free running . 1 disabled: afc is disabled . 2 hold: afc is paused . 3 lock: afc locks after the preamble or sync word . the bandwidth of the afc loop can be controlled by the afc _ ki and afc_kp parameters in the radio _ cfg _11 register (address 0x117). the maximum afc pull - in range is automatically set based on the programmed if filter bandwidth ( ifbw in the radio _ cfg _9 register (address 0x11 5). table 39 . ma ximum afc p ull -i n r ange if bandwidth max afc p ull -i n r ange 100 khz 50 khz 150 khz 75 khz 200 khz 100 khz 300 khz 150 khz afc and preamble length the afc require s a certain number of the received preamble bits to correct the frequency error between the transmitter and the receiver. the number of preamble bits required depends on the data rate and whether the afc is locked on detection of the qualified preamble or l ocked on detection of the qualified sync word. this is discussed in more deta il in the recommended receiver settings for 2fsk/gfsk/msk/gmsk section. 08291-156 frequency correlator if filter limiters mixer rfio_1p rfio_1n lna rxdata/ rxclk post-demod filter clock and data recovery i q if rf synthesizer (lo) data_rate[11:0] post_demod_bw[7:0] discrim_bw[7:0] discrim_phase[1:0] ifbw[1:0] (address radio_cfg_9[7:6]) pi control 2 t averaging filter afc system range max_afc_range[7:0] afc_lock_mode[1:0] afc_ki[3:0] (address radio_cfg_11[7:4]) afc_kp[3:0] afc lock sport mode gpios communications processor preamble detect sync word detect preamble_match = 0
adf7023 data sheet rev. c | page 80 of 112 afc readback the f requency error between the received carrier and the receive r local oscillator can be measured when afc is enabled. the error value can be read from the frequency _ error _ readback register ( address 0x372), where each lsb equates to 1 khz. the value is a two s complement number. the frequency _ error _ readback value is valid in the phy_rx state after the afc has been locked. the value is retained in the frequency _ error _ readback register after recovering a packet and transitioning back to the phy_on state . post - de modulator filter a second - order, digital low - pass filter removes excess noise from the demodulated bit stream at the output of the discrimina tor. the bandwidth of this post - demodulator filter is programmable and must be optimized for the users data rate and received modulation type. if the bandwidth is set too narrow, performance degrades due to intersymbol interference (isi). if the bandwidth is set too wide, excess noise degrades the performance of the receiver. fo r optimum performance, the post - demodul ator filter bandwidth should be set close to 0.75 times the data rate (when using fsk/gfsk/msk/gmsk modulation ). the actual bandwidth of the post - demodulator filter is given by post -d emodulator filter bandwidth (khz) = post_demod_bw 2 w here post_demod_bw is set in the radio_cfg_4 register (address 0x110) . clock recovery an oversampled digital clock and d ata r ecovery (cdr) pll is used to resynchronize the received bit stream to a local clock in all mod ulation modes. the maximum symbol rate tolerance of the cdr pll is determined by the number of bit transitions in the transmitted bit stream. for example, during reception of a 010101 preamble, the cdr achieves a maximum data rate tolerance of 3.0%. ho wever, this tolerance is reduced during recovery of the re mainder of the packet where symbol transitions may not be guaranteed to occur at regular intervals during the payload data . to maximize data rate tolerance of the receivers cdr, 8b / 10b encoding or manchester encoding should be enabled , which guarante es a maximum number of contiguous bits in the transmitted bit stream. data whitening can also be enabled on the adf7023 to break up long sequence s of contiguous data bit patterns. using 2 fsk /gfsk /msk/gmsk modulation, it is also possible to tolerate uncoded payload data fields and payload data fields with long run length coding constraints if the data rate tolerance and packe t length are both constrained. more details of cdr operation using uncoded packet formats are discussed in the an - 915 application note . the adf7023s cdr pll is optimized for fast acquisition of the recovered symbols during preamble and typically achie ves bit synchronization within five symbol transitions of preamble. ook demodulation the adf7023 can be configured for ook demodulation by setting demod_scheme = 2 in the radio_cfg_9 register (address 0x115). manchester encoding should be used with ook modulation to ensure optimum performance. ook demodulation is performed using the receivers rssi signal in conjunction with a fully automatic threshold detection circuit, which extracts the optimum ook threshold during preamble and maintains robust packet error performance over the full input power range. the bandwidth of the threshold detection circuit is set by the afc_ki and afc_kp parameter s in the radio_cfg_11 register (address 0x117). the agc loop band - width can be independently optimized for acquisition and trackin g modes during ook reception by setting ook_agc_clk_acq and ook_agc_clk_trk (address 0x35b) , respectively . this demodulation scheme delivers high receiver saturation performance in ook mode. the receiver also supports ook modulation depths of up to 20 db . for optimum performance, the agc and threshold detection circuit should be set to lock after preamble detection by setting agc_lock_mode = 3 in the radio_cfg_7 register (address 0x113) and afc_lock_mode = 3 in the radio_ cfg_10 register (address 0x116 ). the recommended post - demodulator filter bandwidth is 1.6 times the chip rate when using ook demodulation. this can be configured via the post_demod_bw set ting in the radio_cfg_4 register (address 0x110) .
data sheet adf7023 rev. c | page 81 of 112 recommended receiver settings for 2fsk/gfsk/msk/gmsk to optimiz e the adf7023 receiver performance and to ensure the lowest possible packet error rate , it is recommended to use the following configurations : ? set the recommended agc low and high thresholds and the agc clock divide. ? set the recommended afc ki and kp parameters . ? use a preamble length the minimum recommended preamble length . ? when the agc is configured to lock on the sync word a t data rates greater than 200 kbps , it is recommended to set the sync word error tolerance to one bit. the recommended settings for agc, afc, preamble length, and sync word are summari z ed in table 41. recommended agc settings t o optimi z e the receiver for robust packet error rate performance, whe n using minimum preamble length over the full input power range, it is recommended to overwrite the default agc settings in the mcr memory. the recommended settings are as follows: ? agc_high_threshold (address 0x35f) = 0x78 ? agc_low_threshold (address 0x35e) = 0x46 agc_clock_divide (address 0x32f) = 0x0f or 0x19 (depends on the data ra te ; see table 41 ) mcr memory is not retained in phy_sleep ; therefore, t o allow the use of these optimized agc settings in low power mode applications , a static register fix can be used. an example static register fix to write to the agc settings in mcr memory is shown in table 40 . table 40 . example static register f ix for agc s ettings bbram register data description 0x128 (static_reg_fix) 0x2b pointer to bbram address 0x12b 0x12b 0x5e mcr address 0x35e 0x12c 0x46 data to write to mcr address 0x35e (s ets agc low threshold) 0x12d 0x5f mcr address 0x35f 0x12e 0x78 data to wr ite to mcr address 0x35f (sets agc high threshold) 0x12f 0x2f mcr address 0x32f 0x130 0x0f data to write to mcr address 0x3 2f (s ets agc clock divide) 0x131 0x00 ends static mcr register fixes recommended afc settings the bandwidth of the afc loop is controlled by the afc_ki and afc_kp parameters in the radio_cfg_11 register (address 0x117). to ensure optimum af c accuracy while minimi z ing the afc settling time (and thus the required preamble length), the afc_ki and afc_kp parameters should be set as outlined in table 41 . recommended preamble length when afc is locked on pr eamble detection, the minimum preamble length is between 40 and 60 bits depending on the data rate. when afc is set to lock on sync word detection, the minimum preamble length is between 14 and 32 bits, depending on the data rate. when afc and preamble detection are disabled , the minimum preamble length is dependent on the agc settling time and the cdr acquisition time and is between 8 and 24 bits, depending on t he data rate. the required pream ble length for variou s data rates and receiver configuration s is summarized in table 41. recommended sync word tolerance at data rates greater than 200 kbps and when the agc is configured to lock on the sync word , it is recommended to set the sync word error tolerance to one bit ( sync_error_tol = 1). this prevents an agc gain change during sync word reception causing a packet loss by allowing one bit error in the received sync wo rd.
adf7023 data sheet rev. c | page 82 of 112 table 41. summary of recommended agc, afc, preamble l ength , and sync word e rror t olerance for 2fsk/gfsk/msk/gmsk data rate (kbps) freq d eviation (khz) if bw (khz) setup 1 agc 2 afc 3 minimum preamble l ength (b its ) 4 sync word error t olerance (bits) 5 high threshold low threshold clock divide on/off ki kp 300 75 300 1 0x78 0x46 0x0f on 7 3 64 0 2 0x78 0x46 0x19 on 8 3 32 1 3 0x78 0x46 0x19 off 24 1 200 50 200 1 0x78 0x46 0x19 on 7 3 58 0 150 37.5 150 1 0x78 0x46 0x19 on 7 3 54 0 100 25 100 1 0x78 0x46 0x19 on 7 3 52 0 50 12.5 100 1 0x78 0x46 0x19 on 7 3 50 0 38.4 20 100 1 0x78 0x46 0x19 on 7 3 44 0 2 0x78 0x46 0x19 on 7 3 14 0 3 0x78 0x46 0x19 off 8 0 9.6 10 100 1 0x78 0x46 0x19 on 7 3 46 0 3 0x78 0x46 0x19 off 8 0 1 10 100 1 0x78 0x46 0x19 on 7 3 40 0 3 0x78 0x46 0x19 off 8 0 1 setup 1: afc and agc are configured to lock on preamble detection by setting afc_lock_mode = 3 and agc_lock_mode = 3. setup 2: afc and agc are configured to lock on sync word detection by setting afc_lock_mode = 3, agc_lock_mode = 3, and preamble_match = 0. setup 3: afc is disabled and agc is configured to lock on sync word detection by setting afc_lock_mode = 1, agc_lock_mode = 3 , and preamble_m atch = 0. 2 the agc high threshold is configured by writing to the agc_high_threshold register (address 0x35f). the agc low threshold is configured by writing to the agc_low_threshold register (address 0x35e). the agc clock divide is configured by writing to the agc_clock_divide register (address 0x32f). 3 the afc is enabled or disabled by writing to the afc_lock_mode setting in register radio_cfg_10 (address 0x116). the afc ki a nd kp parameters are configured by writing to the afc_kp and afc_ki settings in the radio_cfg_11 register (address 0x117). 4 the transmit preamble length (in bytes) is set by writing to the preamble_len register (address 0x11d). 5 the sync word error tolerance (in bits) is set by writing to the sync_error_tol setting in the sync_control register (address 0x120). recommended receiver settings for ook to e ns ur e robust ook reception , the agc threshold detection , preamble length , and post - demodulator filter bandwidth are recommended to be set as detailed in table 42. table 42 . summary of r ecomm ended s ettings for agc, afc , and p reamble l ength in ook d emodulation data rate (kbps) chip rate (kcps) if bw (khz) agc 1 threshold detection 2 minimum preamble length (b its) post - d emod ulator b andwidth high thresh old low thresh old agc_ lock_ mode ook_ agc_ clk_ acq ook_ agc_ clk_ trk afc _ki afc _kp afc_ lock_ mode 2.4 to 19.2 4.8 to 38.4 100 0x69 0x2d 3 1 2 6 3 3 64 1.6 chip r ate 1 the recommended values for the agc high threshold (agc_high_threshold), ook_agc_clk_acq, and ook_agc_clk_trk are the same as the default values and, therefore, do not need to be set by the host processor. the agc lo w threshold is configured by writing to the agc_low_threshold register (address 0x35e). the agc lock on preamble detection is configured by setting agc_lock_mode = 3 (in register radio_cfg_7, address 0x113) . 2 the afc_ki and afc_kp parameters control the bandwidth of the threshold detection loop in ook demodulation. they are configured by writing to the radio_cfg_11 register (address 0x117). setting afc_lock_mode = 3 configures the ook threshold detection to lock on preamble d etection.
data sheet adf7023 rev. c | page 83 of 112 peripheral features analog- to - digital converter the adf 7023 supports an integrated sar adc for digitization of analog signals that include the analog temperature sensor, the analog rssi level, and an external analog input signal (pin 30 ). the conversion time is typically 1 s. the result of the conver - sion can be read from the adc _ readback _ high regi s ter ( address 0x327), and the adc _ readback _ low register ( address 0x328). the adc readback is an 8 - bit value. the signal source for the adc input is selected via the adc _ config _ low register ( address 0x359). in the phy_rx state, the source is automatically set to the analog rssi. the adc is automatically enabled in phy_rx. in other radio states , the host processor must enable the adc by setting powerdown_rx ( address 0x324) = 0x10. to perform a n adc readback, the fol lowing procedure should be completed : 1. read adc _ readback _ high . this initializes an adc readback. 2. read adc _ readback _ low . this returns adc _ readback [1 :0] of the adc sample. 3. read adc _ readback _ high . this returns adc _ readback [7: 2 ] of the adc sample. temperature s ensor the integrated temperature sensor has an operating range between ?40c and +85c. t o enable readback of the temperature sensor in phy_off, phy_on , or phy_tx , the following registers must be set : 1. set powerdown_rx ( address 0x324) = 0x10 = 0x10. this enables the adc. 2. set powerdown_aux ( address 0x325) = 0x02. this enables the temperature sensor. 3. set adc _c onfig_ l ow ( address 0x359) = 0x08. this sets the adc input to the temperature sensor. the temperature is determined from the adc readback value using t he following formula: temperature (c) = 0.9474 ( adc_readback[7:0] C calibration value[7:0] ) + t calibration the calibration value[7:0] is determined via an adc readback at a single known temperature , t calibration . when this correction is applied, the temperature sensor is accurate to +7 c to ? 4 c over the full operating temperature range. test dac the test dac allows the output of the post - demodulator filter to be viewed externally. it takes the 16 - bit filter output and converts it to a high frequency, single - bit output using a second order - converter. the output can be viewed on the gp0 pin. this signal, when filtere d appropriately, can be used to ? monitor the signal at the post - demodulator filter output ? measure the demodulator output snr ? construct an eye diagram of the received bit stream to measure the received signal quality ? implement analog fm demodulation to enable the test dac , the gpio _ configure setting ( address 0x3fa) should be set to 0xc9. the test _ dac _ gain setting ( address 0x3fd) should be set to 0x00. the test dac signal at the gp0 pin can be filtered with a three -stage, low - pass rc filter to reconstruct the demodulated signal. for more information, see the an - 852 a pplication n ote. transmit test modes there are two transmit test modes that are enabled by setting the va r _ tx _ mode parameter ( address 0x00d in packet ram memory ), as described in table 43 . va r _ tx _ mode should be set before entering the phy_tx state . table 43 . transmit te st m odes var _ tx _ mode mode 0 default ; n o transmit test mode 1 transmit random data continuously 2 transmit the preamble continuously 3 transmit the carrier continuously 4 to 255 r eserved silicon revision rea dback the product code and silicon revision code can be read from the packet ram memory as described in table 44 . the values of the product code and silicon revision code are valid only on power - up or wake - up from the phy_sleep state because the communications processor overwrites these values on transitioning from the phy_on state. table 44 . product code and silicon revision code packet ram location description 0x00 1 product c ode, most significant byte = 0x70 0x002 product c ode, least significant byte = 0x23 0x003 silicon revision code, most significant byte 0x004 silicon revision code least significant byte
adf7023 data sheet rev. c | page 84 of 112 applications informa tion application circuit a typical application circuit for the adf7023 is shown in figure 110 . all external components required for operation of the device, excluding supply decoupling capacitors , are shown. this example circuit uses a combined single - ended pa and lna match. further details on matching topologies and different host processor interfaces are given in the following sections . figure 110 . typical adf7023 application circuit di agram 08291-039 ad f 7023 creg rf1 p a/ln a ma tch rb ias creg rf2 rf io _1p rf io _1n rfo2 v dd bat2 nc cs mosi sclk miso irq_gp3 gp2 gp1 gp0 gp4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vdd controller 32kh z xtal (optional) 26 mhz xtal gpio mosi sclk miso irq g nd pad creg d ig 1 dguard xosc 26 n xosc 26 p cw akeu p creg synth vc og uar d creg vco creg d ig 2 vdd v dd xosc32kp_gp5_ a tb1 xosc32kn_at b2 vddb a t1 adcin_ a tb3 a tb4 adcvref an te nn a connect io n har monic filter
data sheet adf7023 rev. c | page 85 of 112 host p rocessor interface the interface , when using packet mode , between the adf7023 and the host processor is shown in figure 111 . in packet mode , all communication between the host processor and the adf7023 occurs on the spi interface and the irq_gp3 pin. the interface between the adf7023 and the host processor in sport mode is shown in figure 112 . in sport mode, the transmit and receive data interface consists of the gp0, gp1 , and gp2 pin s and a separate int errupt is available on gp4, while t he spi interface is used for memory access and issuing of commands. figure 111 . processor interface in packet m ode figure 112 . processor i nterface in s port m ode pa/lna matching the ad7023 has a differential lna and both a single - ended pa and differential pa. this flexibility allows numerous possibil - ities in interfacing the adf7023 to the antenna. combined single - ended pa and lna match th e combined single - ended p a and lna match allows the transmit and receive paths to be combined without the use of an external transmit/receive switch. the matching network design is shown in figure 113 . the differential lna match is a five - element discrete balun giving a single - ended input. the single - ended pa output is a three - element match consisting of the choke inductor to the cregrf2 regulated supply and a n inductor and capacitor series . the lna and pa paths are combined , and a t - stage harmonic filter provides attenuation of the transmit harmonics. in a combined match , the off impedances of the pa and lna must be considered. this can lead to a small loss in transmit power and degradation in receiver sensitivity in comparison with a separate single - ended pa and lna match. however, with optimum matching, the typical loss in transmit power is <1db , and the degradation in sensitivity is < 1db when compared with a separate pa and lna matching t opology. figure 113 . combined s ingle - ended pa and lna m atch separate single -e nded pa/lna match the separate single - ended pa and lna matching configuration is illustrated in figure 114 . the network is the same as the combined matching network shown in figure 113 except that the transmit and receive paths are separate. an external transmit/receive antenna switch can be used to combine the transmit and receive paths to allow connection to an antenna. in designing this matching network , it is not necessary to consider the off impedances of the pa and lna , and , thus , achieving an optimum match is less complex than with the combined single - ended pa and lna match. figure 114 . separate s ingle -e nded pa and lna match adf7023 08291-158 cs mosi sclk miso irq_gp3 gp2 gp1 gp0 gp4 24 v dd 23 22 21 20 19 18 17 25 controller gpio mosi sclk miso irq 08291-159 cs mosi sclk miso irq_gp3 gp2 gp1 gp0 gp4 24 23 22 21 20 19 18 17 25 controller gpio irq mosi sclk miso irq txrxclk txd at a rxd at a v dd adf7023 match creg rf2 adf7023 rf io _1p rf io _1n rfo2 3 4 5 6 an te nn a connect io n 08291-160 har monic filter lna match pa match creg rf2 adf7023 rf io _1p rf io _1n rfo2 3 4 5 6 tx rx 08291-161 har monic filter
adf7023 data sheet rev. c | page 86 of 112 combined differential pa/lna match in this matching topology , the single- ended pa is not used. the differential pa and lna match comprises a five - element discrete balun giving a single - ended input/output as illustrated in figure 115. the harmonic filter is used to minimize the rf harmonics from the differential pa. figure 115 . combined d ifferential pa and lna match transmit antenna diversity transmit antenna diversity is possible using the differential pa and single - ended pa. the required matching network is shown in figure 116 . figure 116 . matching topology for t ransmit antenna d iversity support for external pa and lna control the adf7023 provides independent control signals for an external pa or lna. if the ext _ pa _ en bit is set to 1 in the mode _ control register (address 0x11a), the external pa control signal is logic high while the adf7023 is in the phy_tx state and logic low while in any other state. if the ext _ lna _ en bit is set to 1 in the mode _ control register (address 0x11a), the external lna control signal is logic high while the adf7023 is in the phy_rx state and logic low while in any other state. the external pa and lna control signals can be configured using the ext_pa_lna_ atb_config setting (address 0x139 , bit[7] ) as described in table 45 . table 45 . configuration of the e xternal pa and lna control s ignals ext_pa_lna_ atb_ config configuration 1 adcin_atb3 and atb4 used for control of external pa and ext ernal lna , respectively (1.8 v logic outputs). 0 xosc32kp_gp5_atb1 and xosc32kn_atb2 used for control of ext ernal pa and ext ernal lna , respectively (v dd logic outputs). creg rf2 adf7023 rf io _1p rf io _1n rfo2 3 4 5 6 antenna connection 08291-162 har monic filter differential pa and lna match single-ended pa match creg rf2 adf7023 rf io _1p rf io _1n rfo2 3 4 5 6 tx (single- ended pa) tx (differential pa) and rx 08291-163 har monic filter har monic filter
data sheet adf7023 rev. c | page 87 of 112 command reference table 46. radio controller c ommands command code description cmd_sync 0xa2 this is an optional command. it is not necessary to use it during device initialization cmd_phy_off 0xb0 performs a transition of the device into the phy_off state. cmd_phy_on 0xb1 performs a transition of the device into the phy_on state. cmd_phy_rx 0xb2 performs a transition of the device into the phy_rx state. cmd_phy_tx 0xb5 performs a transition of the device into the phy_tx state. cmd_phy_sleep 0xba performs a transition of the device into the phy_sleep state. cmd_config_dev 0xbb configures the radio parameters based on the bbram values. cmd_get_rssi 0xbc performs an rssi measurement . cmd_bb_cal 0xbe performs a calibration of the if filter . cmd_hw_reset 0xc8 performs a full hardware reset. the device enters the phy_sleep state. cmd_ram_load_init 0xbf prepares the program ram for a firmware module download . cmd_ram_load_done 0xc7 performs a reset of the communications processor after download of a firmware module to program ram . cmd_ir_cal 1 0xbd initiates an image rejection calibration routine. cmd_aes_encrypt 2 0xd0 perform s an aes encryptio n on the transmit payload data stored in packet ram. cmd_aes_decrypt 2 0xd 2 perform s an aes decryptio n on the received payload data stored in packet ram. cmd_aes_decrypt_init 0xd 1 initializes the internal variables required for aes decryption . cmd_ rs _ encode_init 3 0xd 1 initializes the internal variables required for the reed solomon encoding. cmd_ rs _encode 3 0xd 0 calculates and appends the reed solomon check bytes to the transmit payload data stored in packet ram. cmd_ rs _ decode 3 0xd2 performs a reed solomon error correction on the received payload data stored in packet ram . 1 the image rejection calibration firmware module must be loaded to program ram for this command to be functional. 2 the aes firmware module must be loaded to program ram for this command to be functional. 3 the reed solomon coding firmware module must be loaded to program ram for this command to be functional. table 47 . spi c ommands command code description spi_mem_wr 00011xxxb = 0x18 (packet ram) 0x19 (bbram) 0x1b (mcr) 0x1 e (program ram) write s data to bbram , mcr , or packet ram memory sequentially. an 11 - bit address is used to identify memory locations. the most significant three bits of the address are incorporated in to the command (xxxb). this command is followed by the remaining eight bits of the address, which are subseque ntly followed by the data bytes to be written . spi_mem_rd 00111xxxb = 0x38 (packet ram) 0x39 (bbram) 0x3b (mcr) read s data from bbram , mcr , or packet ram memory sequentially. an 11 - bit address is used to identify memory locations. the most significant three bits of the address are incorporated into the command (xxxb). this command is followed by the remaining eight bits of the address, which are subsequ ently followed by the appropriate number of spi_nop commands. spi_memr_wr 00001xxxb = 0x08 (packet ram) 0x09 (bbram) 0x0b (mcr) write s data to bbram , mcr , or p acket ram memory non sequentially . spi_memr_rd 00101xxxb = 0x28 (packet ram) 0x29 (bbram) 0x2b (mcr) read s data from bbram, mcr , or p acket ram memory non sequentially . spi_nop 0xff no operation. use for dummy writes when polling the status word; u sed also as dummy data when performing a memory read.
adf7023 data sheet rev. c | page 88 of 112 register maps table 48 . battery backup memory (bbram) address (hex) register retained in phy_sleep r/w group 0x100 interrupt _ mask _0 yes r/w mac 0x101 interrupt _ mask _1 yes r/w mac 0x102 number _ of _ wakeups _0 yes r/w mac 0x103 number _ of _ wakeups _1 yes r/w mac 0x104 number _ of _ wakeups _ irq _ threshold _0 yes r/w mac 0x105 number _ of _ wakeups _ irq_threshold _1 yes r/w mac 0x106 rx_dwell _ time yes r/w mac 0x107 parmtime _ divider yes r/w mac 0x108 swm _rssi_ thresh yes r/w phy 0x109 channel _ freq _0 yes r/w phy 0x10a channel _ freq _1 yes r/w phy 0x10b channel _ freq _2 yes r/w phy 0x10c radio _ cfg _0 yes r/w phy 0x10d radio _ cfg _1 yes r/w phy 0x10e radio _ cfg _2 yes r/w phy 0x10f radio _ cfg _3 yes r/w phy 0x110 radio _ cfg _4 yes r/w phy 0x111 radio _ cfg _5 yes r/w phy 0x112 radio _ cfg _6 yes r/w phy 0x113 radio _ cfg _7 yes r/w phy 0x114 radio _ cfg _8 yes r/w phy 0x115 radio _ cfg _9 yes r/w phy 0x116 radio _ cfg _10 yes r/w phy 0x117 radio _ cfg _11 yes r/w phy 0x118 image _ reject _ cal _ phase yes r/w phy 0x119 image _ reject _ cal _ amplitude yes r/w phy 0x11a mode _ control yes r/w phy 0x11b p reamble _ match yes r/w packet 0x11c s ymbol _ mode yes r/w packet 0x11d p reamble _ len yes r/w packet 0x11e crc _p oly _0 yes r/w packet 0x11f crc _p oly _1 yes r/w packet 0x120 sync _c ontrol yes r/w packet 0x121 s ync _b yte _0 yes r/w packet 0x122 s ync _b yte _1 yes r/w packet 0x123 s ync _b yte _2 yes r/w packet 0x124 tx _base_a dr yes r/w packet 0x125 rx _base_a dr yes r/w packet 0x126 packet _ length _c ontrol yes r/w packet 0x127 packet _ length _m ax yes r/w packet 0x12 8 static_reg_fix yes r/w phy 0x12 9 a ddress _m atch _o ffset yes r/w packet 0x12 a to 0x13 7 a ddress filtering yes r/w packet 0x138 rssi_wait_time yes r/w phy 0x139 testmodes yes r/w mac 0x13a transition_clock_div yes r/w phy 0x13b to 0 x13d reserved ; set to 0x00 not applicable r /w not applicable 0x13e rx_synth_lock_time yes r/w phy 0x13f tx_synth_lock_time yes r/w phy
data sheet adf7023 rev. c | page 89 of 112 table 49 . modem configuration memory (mcr) address (hex) register retained in phy_sleep r/w 0x307 pa _ level _ mcr no r/w 0x30c wuc _ config _ high no w 0x30d wuc _ config _ low no w 0x30e wuc _ value _ high no w 0x30f wuc _ value _ low no w 0x310 wuc _ flag _ reset no r/w 0x311 wuc _ status no r 0x312 rssi_readback no r 0x315 max _ afc _ range no r/w 0x319 image _ reject _ cal _ config no r/w 0x322 chip _ shutdown no r/w 0x324 powerdown_rx no r/w 0x325 powerdown _ aux no r/w 0x327 adc _ readback _ high no r 0x328 adc _ readback _ low no r 0x32d battery_monitor_threshold_voltage no r/w 0x32e ext_uc_clk_divide no r/w 0x32f agc_clk_divide no r/w 0x336 interrupt_source_0 no r /w 0x337 interrupt_source_1 no r /w 0x338 calibration_control no r/w 0x339 calibration_status no r 0x345 rxbb_cal_calwrd_readback no r 0x346 rxbb_cal_calwrd_overwrite no rw 0x34f rcosc_cal_readback_high no r 0x350 rcosc_cal_readback_low no r 0x359 adc_config_low no r/w 0x35a adc_config_high no r/w 0x35b agc_ook_control no r/w 0x35c agc_config no r/w 0x35d agc_mode no r/w 0x35e agc_low_threshold no r/w 0x35f agc_high_threshold no r/w 0x360 agc_gain_status no r 0x361 agc_adc_word no r 0x372 frequency_error_readback no r 0x3cb vco_band_ovrw_val no r/w 0x3cc vco_ ampl _ovrw_val no r/w 0x3cd vco_ovrw_en no r/w 0x3d0 vco_cal_cfg no r/w 0x3d2 osc_config no r/w 0x3da vco_band_readback no r 0x3db vco_ ampl_readback no r 0x3f8 analog_test_bus no r/w 0x3f9 rssi_tstmux_sel no r/w 0x3fa gpio_configure no r/w 0x3fd test_dac_gain no r/w
adf7023 data sheet rev. c | page 90 of 112 table 50 . packet ram memory address register r/w 0x000 var _ command r/w 0x00 1 1 product c ode, most significant byte = 0x70 r 0x002 1 product c ode, least significant byte = 0x23 r 0x003 1 silicon revision code, most significant byte r 0x004 1 silicon revision code , least significant byte r 0x00 5 to 0x00b r eserved r 0x00d var _ tx _ mode r/w 0x00e to 0x00f r eserved r 1 only valid on powe r- up or wake - up from the phy_sleep state because the communications processor overwrites these values on exit from the phy_on state. bbram register descr iption table 51 . 0x100: interrupt _ mask _0 bit name r/w description [7] interrupt_num_wakeups r/w interrupt when the number of wuc wake - ups (number_of_wakeups[15:0]) has reached the threshold (number_of_wakeups_irq_threshold[15:0]) 1: i nterrupt enabled; 0: i nterrupt disabled [6] interrupt_swm_rssi_det r/w interrupt when the measured rssi during smart wake mode has exceeded the rssi threshold value (s wm _rssi_thres h , address 0x108) 1: i nterrupt enabled; 0: i nterrupt disabled [5] interrupt_aes_done r/w interrupt when an aes encryption or decryption command is complete; a vailable only when the aes firmware module has been loaded to the adf7023 pr ogram ram 1: i nterrupt enabled; 0: i nterrupt disabled [4] interrupt_tx_eof r/w interrupt when a packet has finished transmitting 1: i nterrupt enabled; 0: i nterrupt disabled [3] interrupt_address_match r/w interrupt when a received packet has a valid address match 1: i nterrupt enabled; 0: i nterrupt disabled [2] interrupt_crc_correct r/w interrupt when a received packet has the correct crc 1: i nterrupt enabled; 0: i nterrupt disabled [1] interrupt_sync_detect r/w interrupt when a qualified sync word has been detected in the received packet 1: i nterrupt enabled; 0: i nterrupt disabled [0] interrupt_premable_detect r/w interrupt when a qualified preamble has been detected in the received packet 1: i nterrupt enabled; 0: i nterrupt disabled t able 52 . 0x101: interrupt _ mask _1 bit name r/w description [7] battery_alarm r/w interrupt when the b at tery voltage has dropped below the threshold value ( battery_monitor_threshold_voltage , address 0x32d) 1: i nterrupt enabled; 0: i nterrupt disabled [6] cmd _ready r/w interrupt when the communications processor is ready to load a new command ; mirrors the c md_ready bit of the status word 1: i nterrupt enabled; 0: i nterrupt disabled [5] reserved r/w [4] wuc_timeout r/w interrupt when the wuc has timed out 1: i nterrupt enabled; 0: i nterrupt disabled [3] reserved r/w [2] reserved r/w [1] spi_ready r/w interrupt when the spi is ready for access 1: i nterrupt enabled; 0: i nterrupt disabled [0] cmd_finished r/w interrupt when the communications processor ha s finished performing a command 1: i nterrupt enabled; 0: i nterrupt disabled
data sheet adf7023 rev. c | page 91 of 112 table 53 . 0x102: number _ of _ wakeups _0 bit name r/w description [7:0] number _ of _ wakeups [7:0] r/w bits[7:0] of [15:0] of an internal 16 - bit count of the number of wake - ups ( wuc timeouts) the device has gone through. it can be initialized to 0x0000. table 54 . 0x103: number _ of _ wakeups _1 bit name r/w description [7:0] number _ of _ wakeups [15:8] r/w bits [15:8] of [15:0] of an internal 16 - bit count of the number of wuc wake - ups the device has gone through. it can be initialized to 0x0000. table 55 . 0x104: number _ of _ wakeups _ irq _ threshold _0 bit name r/w description [7:0] number _ of _ wakeups _ irq _ threshold [7:0] r/w bits [7:0] of [15:0] (see table 56) . t he threshold for the number of wake - ups ( wuc timeouts). it is a 16 - bit count threshold that is compared against the number _ of _ wakeups parameter . when this threshold is exceeded , the device wakes up in the phy_off state and optionally generates interrupt _ num _ wakeups . table 56 . 0x105: number _ of_wakeups _ irq _ threshold _1 bit name r/w description [ 7 : 0 ] number _ of _ wakeups _ irq _ threshold [15:8] r/w bits[15:8] of [15:0] (see table 55 ). table 57 . 0x106: rx _ dwell _ time bit name r/w description [7:0] rx _ dwell _ time r/w when the wuc is used and swm is enabled, the radio powers up and enables the receiver on the channel defined in the bbram and listens for this period of time. if no preamble pattern is detected in this period, the device goes back to sleep. receive dwell t ime (s) = rx_dwell_time ivider parmtime_d 128 mhz6.5 table 58 . 0x107: parmtime _ divider bit name r/w description [7:0] parmtime _ divider r/w units of time used to define the rx _ dwell _ time time period. timer tick r ate = mhz6.5 128 ivider parmtime_d a value of 0x33 give s a clock of 995.7 hz or a period of 1.004 ms . table 59 . 0x108: swm_rssi _ thresh bit name r/w description [7:0] swm _rssi_ thresh r/w this s ets the rssi threshold when in s mart wake m ode with rssi detection enabled. threshold (dbm) = swm _ rssi _ thresh ? 107 table 60 . 0x109: channel _ freq _0 bit name r/w description [7:0] channel _ freq [7:0] r/w the rf channel frequency in hertz is set according to 16 2 ) ( 0] : eq[23 channel_fr pfd f (hz) frequency = where f pfd is the pfd frequency and is equal to 26 mhz.
adf7023 data sheet rev. c | page 92 of 112 table 61 . 0x10a: channel _ freq _1 bit name r/w description [7:0] channel _ freq [15:8] r/w see the channel _ freq _0 description in table 60 . table 62 . 0x10b: channel _ freq _2 bit name r/w description [7:0] channel _ freq [23:16] r/w see the channel _ freq _0 description in table 60 . table 63 . 0x10c: radio _ cf g _0 bit name r/w description [7:0] data _ rate [7:0] r/w the data rate in bps is set according to 100 [11:0] = data_rate (bps)ratedata table 64 . 0x10d: radio _ cfg _1 bit name r/w description [7:4 ] f req _ deviation [11:8 ] r/w see the freq _ deviation description in radio _ cfg _2 ( table 65 ). [3:0] data _ rate [11:8] r/w see the data _ rate description in radio _ cfg _0 ( table 63 ). table 65 . 0x10e: radio _ cfg _2 bit name r/w description [7:0] f req _ deviation [7:0] r/w the binary level 2fsk /gfsk/msk/gmsk frequency deviation in hertz (defined as the frequency difference between carrier frequency and 1/0 tones) is set according to 100 = 0] : [11 tion freq_devia (hz) deviation frequency table 66 . 0x10f: radio _ cfg _3 table 67 . 0x110: radio _ cfg _4 table 68 . 0x111: radio _ cfg _5 bit name r/w description [7:0] r eserved r/w set to zero . table 69 . 0x112: radio _ cfg _6 bit name r/w description [7:2] synth _ lut _ config _0 r/w if synth_lut_control (address 0x113, table 70 ) = 0 or 2, set synth_lut_config_0 = 0. if synth_lut_control = 1 or 3, this setting allows the receiver pll loop bandwidth to be changed to optimize the receiver local oscillator phase noise. [1 :0] discrim _ phase [1:0] r/w the discrim_phase value sets the phase of the correlator demodulator. see the 2fsk/gfsk/msk/gmsk demodulation section for the steps requi red to set the discrim_phase value . bit name r/w description [7:0] discrim _ bw [7:0] r/w the discrim_bw value sets the bandwidth of the correlator demodulator. see the 2fsk/gfsk/msk/gmsk demodulation section for the steps required to set the discrim_bw va lue. bit name r/w description [7:0] post_ demod _ bw [7:0] r/w for optimum performance, the post - demodulator filter bandwidth should be set close to 0.75 times the data rate. the actual bandwidth of the post - demod - ulator filter is given by post -d emodulator filter bandwidth (khz) = post_demod_bw 2 the range of post_demod_bw is 1 to 255.
data sheet adf7023 rev. c | page 93 of 112 table 70 . 0x113: radio _ cfg _7 bit name r/w description [7:6] agc _ lock _ mode r/w set to 0: free running 1: manual 2: hold 3 : lock after preamble /sync word (only locks on a sync word if preamble_ match = 0) [5:4] s ynth _ lut _c ontrol r/w by default , the synthesizer loop bandwidth is automatically selected from lookup tables (lut) in rom memory. a narrow bandwidth is selected in receive to ensure optimum interference rejection, wh ere as in transmit , the bandwidth is selected based on t he data rate and modulation settings . for the majority of applications , these automatically selected pll loop bandwidths are optimum. however, in some applications , it may be necessary to use custom transmit or receive bandwidths , in which case , various options exist, as follows. synth_lut_control description 0 use predefined transmit and receive luts. the luts are automatically selected from rom memory on transitioning into the phy_tx or phy_rx state . 1 use custom receive lut based on synth_ lut_config_0 and synth_lut_config_1. in transmit , the pre defined lut in rom is used. 2 use a custom transmit lut. the custom transmit lut must be written to the 0x10 to 0x18 packet ram locations . in receive, the pre defined lut in rom is used. 3 use a custom receive lut based on synth_ lut_config_0 and synth_lut_config_1 , and use a custom transmit lut. the custom transmit lut must be written to the 0x10 to 0x18 packet ram locations because packet ram memory is lost in the phy_sleep state, the custom lut for transmit must be reloaded to packet ram after waking from the phy_sleep state. [3 :0] synth_lut_config_1 r/w if synth_lut _control = 0 or 2, set synth_lut_config_ 1 to 0. if synth_lut_control = 1 or 3, this setting allows the receiver pll loop bandwidth to be changed to optimize the receiver local oscillator phase noise.
adf7023 data sheet rev. c | page 94 of 112 table 71 . 0x114: radio _ cfg _8 bit name r/w description [7] pa_single_diff_sel r/w pa_single_diff_sel pa 0 single - ended pa enabled 1 differential pa enabled [6:3] pa_ level r/w sets the pa output power . a value of zero sets the minimum rf output power, and a value of 15 sets the maximum pa output power. the pa level can also be set with finer resolution using the pa_level_mcr setting (address 0x307). the pa_level setting is related to the pa_level_mcr s etting by pa_level_mcr = 4 pa_level + 3 pa_ level pa level ( pa_level_mcr) 0 s etting 3 1 s etting 7 2 s etting 11 15 s etting 63 [2:0] pa_ramp r/w se ts the pa ramp rate. the pa ramp s at the programmed rate until it reaches the level indicated by the pa_ level_mcr (address 0x307) setting. the ramp rate is dependent on the programmed data rate. pa_ramp ramp r ate 0 reserved 1 256 codes per data bit 2 128 codes per data bit 3 64 codes per data bit 4 32 codes per data bit 5 16 codes per data bit 6 eight codes per data bit 7 four codes per data bit to ensure the correct pa ramp - up and - down timing, the pa ramp rate has a minimum value based on the data rate and the pa_level or pa_level_mcr settings. this minimum value is described by 0]:11 data_rate[ 0]:cr[5 pa_level_m 10,000 data sheet adf7023 rev. c | page 95 of 112 bit name r/w description [2:0] demod_scheme r/w sets the receiver demodulation scheme. demod_scheme demodulation scheme 0 2fsk/gfsk/msk/gmsk 1 reserved 2 ook 3 to 7 r eserved table 73 . 0x116: radio _ cfg _10 bit name r/w description [7:5] r eserved r/w set to 0. [4] afc _ polarity r/w set to 0 . [3 :2] afc _ scheme r/w set to 2. [1:0] afc_lock_mode r/w sets the afc mode. afc_lock_mode mode 0 free r unning: afc is free running . 1 disabled: afc is disabled . 2 hold afc: afc is paused . 3 lock: afc locks after the preamble or sync word (only locks on a sync word if preamble_match = 0). table 74 . 0x117: radio _ cfg _11 bit name r/w description [7:4] afc _ kp r/w sets the afc pi controller proportional gain in 2fsk/gfsk /msk/gmsk ; the r ecommended value is 0x3. in ook de modulation , this setting is used to control the ook threshold loo p ; the r ecommended value is 0x3 . afc_kp p roportional g ain 0 2 0 1 2 1 2 2 2 15 2 15 [3:0] afc_ki r/w sets the afc pi controller integral gain in 2fsk/gfsk/msk/gmsk; the r ecommended value is 0x7. in ook modulation , this setting is used to control the ook threshold loop ; the r ecommended value is 0x6. afc_ki integral g ain 0 2 0 1 2 1 2 2 2 15 2 15 table 75 . 0x118: image _ reject _ cal _ phase bit name r/w description [7] r eserved r/w set to 0 [6:0] image _ reject _ cal _ phase r/w sets the i/q phase adjustment table 76 . 0x119: image _ reject _ cal _ amplitude bit name r/w description [7] r eserved r/w set to 0 [ 6 : 0 ] image _ reject _ cal _ amplitude r/w sets the i/q amplitude adjustment
adf7023 data sheet rev. c | page 96 of 112 table 77 . 0x11a: mode _ control bit name r/w description [7] swm _ en r/w 1: s mart wake m ode enabled . 0: s mart wake m ode disabled . [6] bb_ cal r/w 1: if f ilter calibration enabled . 0: if f ilter calibration disabled . if filter calibratio n is automatically performed on the transition f r om the phy_off state to the phy_on state if this bit is set. [5] swm _rssi_ qual r/w 1: rssi qualify in low power mode enabled . 0: rssi qualify in low power mode disabled . [4] tx_to_rx _ auto_ turnaround r/w if tx_to_rx _ auto_ turnaround = 1, the device automatically transitions to the phy_rx state at the end of a packet transmission, on the same rf channel frequency. if tx_to_rx _ auto_ turnaround = 0, this operation is disabled. tx_to_rx _ auto_ turnaround is only available in p acket mode. [3] rx_to_tx _ auto_ turnaround r/w if rx_to_tx _ auto_ turnaround = 1 , the device automatically transitions to the phy_ t x state at the end of a valid packet reception , on the same rf channel frequency. if rx_to_tx _ auto_ turnaround = 0, this operation is disabled. rx_to_tx _ auto_ turnaround is only available in p acket mode. [2] custom _ trx _ synth _ lock _ time _ en r/w 1: u se the custom synthesizer lock time defined in register 0x 1 3e and register 0x 1 3f . 0 : default synthesizer lock time. [1] ext _ lna _ en r/w 1: e xternal lna enable signal on atb4 is enabled. the signal is logic high while the adf7023 is in the phy_rx state and logic low while in any other non sleep state. 0: e xternal lna enable signal on atb4 is disabled. [0] ext _ pa _ en r/w 1: e xternal pa enable signal on atb3 is enabled. the signal is logic high while the adf7023 is in the phy_tx state and l ogic low while in any other non sleep state. 0: e xternal pa enable signal on adcin_ atb3 is disabled. table 78 . 0x11b: preamble _ match b it name r/w description [7 :4] r eserved r/w set to 0 [3:0] preamble_match r/w preamble_match description 12 0 errors allowed. 11 one erroneous bit - pair allowed in 12 bit - pairs. 10 two erroneous bit - pairs allowed in 12 bit - pairs. 9 three erroneous bit - pairs allowed in 12 bit - pairs. 8 four erroneous bit - pairs allowed in 12 bit - pairs. 0 preamble detection disabled. 1 to 7 not recommended. 13 to 15 reserved.
data sheet adf7023 rev. c | page 97 of 112 table 79 . 0x11c: symbol _ mode bit name r/w description [7] r eserved r/w set to 0. [6] manchester _ enc r/w 1: manchester encoding and decoding enabled . 0: manchester encoding and decoding disabled . [5] prog _ crc _ en r/w 1: p rogrammable crc selected. 0: default crc selected . [4] eight _ ten _ enc r/w 1: 8b/10b encoding and decoding enabled . 0: 8b/10b encoding and decoding disabled . [3] data _ whitening r/w 1: d ata whitening and de whitening enabled . 0: d ata whitening and de whitening disabled . [2:0] symbol_length r/w symbol_length description 0 8- bit (recommended except when 8b/10b is being used). 1 10 - bit (for 8b/10b encoding) . 2 to 7 reserved . table 80 . 0x11d: preamble _ len bit name r/w description [7:0] preamble _ len r/w length of preamble in bytes. example : a value of decimal 3 results in a preamble of 24 bits. table 81 . 0x11e: crc_ poly _0 bit name r/w description [7:0] crc _ poly [7:0] r/w lower byte of crc _ poly [15:0], which sets the crc polynomial. table 82 . 0x11f: crc _ poly_1 bit name r/w description [7:0] crc _ poly [15:8] r/w upper byte of crc _ p o ly [15:0] , which sets the crc polynomial. see the packet mode section for more details on how to configure a crc polynomial . table 83 . 0x120: sync _ control bit name r/w description [7:6] sync _ error _ tol r/w sets the sync word error tolerance in bits. sync_error_tol bit e rror t olerance 0 0 bit errors allowed . 1 one bit error allowed . 2 two bit error s allowed . 3 three bit error s allowed . [5] r eserved r/w set to 0. [4:0] sync_word_length r/w se ts the sync word length in bits; 24 bits is the maximum. note that the sync word matching length can be any value up to 24 bits, but the transmitted sync word pattern is a multiple of eight bits. therefore , for non - byte - length sync words, the transmi tted sync pattern should be filled out with the preamble pattern. sync_word_length length in b its 0 0 1 1 24 24
adf7023 data sheet rev. c | page 98 of 112 table 84 . 0x121: sync _ byte _0 bit name r/w description [7:0] sync _ byte [ 23:16 ] r/w upper byte of the sync word pattern. the sync word pattern is transmitted most significant bit first starting with sync _ byte _0 . for non byte length sync words , the reminder of the least significant byte should be stuffed with the preamble. if sync _ word _ length le ngth is >16 bits , sync _ byte _0, sync _b yte _1 , and sync _ byte _2 are all transmitted for a total of 24 bits. if sync _ word _ length is between 8 and 15 , sync _ byte _1 and sync _ byte _2 are transmitted. if sync _ word _ length is between 1 and 7 , sync _ byte _2 is transmitted for a total of eight bits. if the sync word length is 0 , no sync bytes are transmitted. table 85 . 0x122: sync _ byte _1 bit name r/w description [7:0] sync _ byte [15:8] r/w mid dle byte of the sync word pattern. table 86 . 0x123: sync _ byte _2 bit name r/w description [7:0] sync _ byte [ 7:0 ] r/w lower byte of the s ync word pattern. table 87 . 0x124: tx _ base _ adr bit name r/w description [7:0] tx _base_ adr r/w address in p acket ram of the transmit packet. this address indicates to the comm unication s processor the location of the first byte of the transmit packet . table 88 . 0x125: rx _ base _ adr bit name r/w description [7:0] rx _base_ adr r/w address in p acket ram of the receive packet. the comm unication s processor write s any qualified received packet to p acket ram, starting at this memory location. table 89 . 0x126: packet _ length _ control bit name r/w description [7] data _ byte r/w over - the - air arrangement of each transmitted p acket ram byte. a b yte is transmitted either msb or lsb first. the same setting should be used on the tx and rx side s of the link. 1: d ata byte msb first . 0: d ata byte lsb first . [6] packet _ len r/w 1: f ixed packet length mode. fixed packet length in t x and r x modes , given by packet _ leng th_ max . 0: variable packet length mode. in r x mode , packet length is given by the first byte in packet ram. in t x mode , the packet length is given by packet _ leng th_ max . [5] crc _ en r/w 1: a ppend crc in transmit mode. check crc in receive mode. 0: n o crc addition in transmit mode. no crc check in receive mode. [4:3] data _ mode r/w sets the adf7023 to packet mode or sport mode for transmit and receive data. data_mode description 0 packet mode enabled. 1 sport mode enabled. gp4 interrupt enabled on preamble detection. rx data enabled on preamble detection. 2 sport mode enabled. gp4 interrupt enabled on sync word detection. rx data enabled on preamble detection. 3 unused.
data sheet adf7023 rev. c | page 99 of 112 bit name r/w description [2:0] length _ offset r/w offset value in bytes that is added to the received packet length field value (in variable length packet mode) so that the communications processor knows the correct number of bytes to read . the communications processor calculates the actual received payload length as rx p ayload l ength = l ength + length_offset ? 4 where l ength is the length field (the first byte in the received payload). table 90 . 0x127: packet _ length _ max bit name r/w description [7:0] packet _ length _ max r/w if variable packet length mode is used ( packet _ len gth _ control = 0), packet _ length _ max sets the maximum receive packet length in bytes. if fixed packet length mode is used ( packet _ len gth _ control = 1), packet _ length _ max sets the length of the fixed transmit and receive packet in bytes. note that the packet length is defined as the number of bytes from the end of the sync word to the start of the crc. it also does not include the length _ offset value . table 91 . 0x128: static _ reg _ fix bit name r/w description [7:0] static_ reg_fix r/w the adf7023 has the ability to implement automatic static register fixes from bbram memory to mcr memory . this feature allows a maximum of nine mcr registers to be programmed via bbram memory. this feature is useful if mcr registers must be configured for optimum receiver performance in low power mode. the static_reg_fix value is an address pointer to any bbram memory address between 0x12a and 0x13d. for example, to point to bbram address 0x12b, set static_reg_fix = 0x2b. ? if static_reg_fix = 0x00, then static register fixes are disabled. ? if static_reg_fix is nonzero, the communications processor looks for the mcr address and corresponding data at the bb ram address beginning at static_reg_fix. example: write 0x46 to mcr register 0x35e and write 0x78 to mcr register 0x35f. set static_reg_fix = 0x2b. bbram register data description 0x128 (static_reg_fix) 0x2b pointer to bbram address 0x12b 0x12b 0x5e mcr address 1 0x12c 0x46 data to write to mcr address 1 0x12d 0x5f mcr address 2 0x12e 0x78 data to write to mcr address 2 0x12f 0x00 ends static mcr register fixes t able 92 . 0x129: address _ match _ offset bit name r/w description [7:0] address _ match _ offset r/w location of first byte of address information in p acket ram table 93 . 0x12a: address_length bit name r/w description [ 7 :0] address_ length r/w number of bytes in the first address field ( n adr _ 1 ). set to zero if address filtering is not being used. table 94. 0x12 b to 0x13 7 : a ddress f iltering (or static register fix ) address bit r/w description 0x12 b [7:0] r/w address 1 m atch b yte 0 . 0x12 c [7:0] r/w address 1 m ask b yte 0 . 0x12 d [7:0] r/w address 1 match b yte 1 . 0x12 e [7:0] r/w address 1 m ask b yte 1 . [7:0] r/w address 1 match b yte n adr _ 1 . [7:0] r/w address 1 mask b yte n adr _ 1 . [7:0] r/w 0x00 to end or n umber of bytes in the second address field (n adr _ 2 )
adf7023 data sheet rev. c | page 100 of 112 table 95 . 0x138: rssi_wait_time bit name r/w description [7:0] rssi_wait_time r/w settling time in s before taking an rssi measurement in swm or when using cmd_get_rssi. a value of 0xa7 can b e used safely in all situations; however, this can be reduced for particular implementations. table 96 . 0x139: testmodes bit name r/w description [7] ext_pa_ lna_ atb_config r/w 1:atb3 and atb4 used for control of extpa and extlna , respectively ( 1.8 v logic outputs ) . 0:atb1 and atb2 used for control of extpa and extlna, respectively (v dd logic outputs). must also enable external pa/lna in r egister 0x11a . [ 6:4 ] reserved r/w set to 0. [3 ] p er_irq_self_clear r/w 1: automatic clear of interrupt_tx_eof and interrupt_correct_crc . 0: normal operation . [2] per_enable r/w 1: packet error rate enabled . 0: packet error r ate disabled . [1] continuous_tx r/w 1: r estart tx after transmitting a packet . 0: n ormal end of tx . [ 0] continuous_rx r/w 1: r estart rx after transmitting a packet . 0: n ormal end of rx . table 97 . 0x13a: transition_clock_div bit name r/w description [7:0] transition_clock_div r/w 0x00: normal transition times . 0x01: fast transition times. 0x04: normal transition times. else: reserved. table 98 . 0x13e: rx _ synth _ lock _ time bit name r/w description [7 :0] rx _ synth _ lock _ time r/w allows the use of a custom synthesizer lock time counter in receive mode in conjunction with the custom _ trx _ synth _ lock _ time _ en setting in the mode _ control register. applies after vco calibration is complete. each bit equates to a 2 s increment. table 99 . 0x13f: tx _ synth _ lock _ time bit name r/w description [7 :0] tx _ synth _ lock _ time r/w allows the use of a custom synthesizer lock time counter in transmit mode in conjunction with the custom _ trx _ synth _ lock _ time _ en setting in the mode _ control register. applies after vco calibration is complete. each bit equates to a 2 s increment . mcr register description t he mcr register settings are not retained when the device enters the phy_sleep state . table 100 . 0x307 : pa _ level _ mcr bit name r/w reset description [5:0] pa _ level _ mcr r/w 0 power a mplifier l evel. if pa r amp is enabled , the pa ramp s to this target level. the pa level can be set in the 0 to 63 range . the pa level (with less resolution) can also be set via the bbram ; therefore, the mcr setting should be used only if more resolution is required.
data sheet adf7023 rev. c | page 101 of 112 table 101 . 0x30c: wuc _c onfig _h igh bit name r/w reset description [7] r eserved w 0 set to 0 . [6:3] rcosc_coarse_cal_value w 0 rcosc_coarse_cal_value change in rc oscillator frequency coarse tune state 0000 +83% state 10 0001 +66% state 9 1000 +50% state 8 1001 +33% state 7 1100 +16% state 6 1101 0% state 5 1110 ?16% state 4 1111 ?33% state 3 0110 ?50% state 2 0111 ?66% state 1 [2:0] wuc_prescaler w 0 wuc_prescaler 32.768 khz divider tick period 0 1 30.52 s 1 4 122.1 s 2 8 244.1 s 3 16 488.3 s 4 128 3.91 ms 5 1024 31.25 ms 6 8192 250 ms 7 65,536 2000 ms register wuc _ config _ low should never be written to without updating register wuc _ config _ high first. table 102 . 0x30d: wuc _ config _ low bit name r/w reset description [7] r eserved w 0 set to 0 . [6] wuc _ rcosc _ en w 0 1: enable rcosc32k . 0: disable rcosc32k . [5] wuc _ xosc32k _ en w 0 1: enable xosc32k . 0: disable xosc32k . [4] wuc _ clksel w 0 select the wuc timer clock source. 1: rc 32.768 khz oscillator. 0: external crystal oscillator . [3] wuc _ bbram _ en w 0 1: enable power to the bbram during the phy_sleep state. 0: disable power to the bbram during the phy_sleep state. [2:1] r eserved w 0 set to 0 . [0] wuc _ arm w 0 1: enable wake - up on a wuc timeout event . 0: disable wake - up on a wuc timeout event . u pdates to register wuc _ va lu e _ high become effective only after register wuc _ va lu e _ low is written to. table 103 . 0x30e: wuc _ value _ high bit name r/w reset description [7:0] wuc _ timer _ value [15:8] w 0 wuc timer reload value, bits[15:8] of [15:0]. a wake - up event is triggered when the wuc unit is enabled and the timer has counted down to 0. the timer is clocked with the prescaler output rate. an update to this register becomes effective only after wuc _ va lue _ low is written. register wuc _ va lu e _ low should never be written to without updating register wuc _ va lu e _ high first. table 104 . 0x30f: wuc _ value _ low bit name r/w reset description [7:0] wuc _ timer _ value [7:0] w 0 wuc timer reload value, bits[7:0] of [15:0]. a wake - up event is triggered when the wuc unit is enabled and the timer has counted down to 0. the timer is clocked with the prescaler output rate.
adf7023 data sheet rev. c | page 102 of 112 table 105 . 0x310: wuc _ flag _ reset bit name r/w reset description [1] wuc_rcosc_cal_en r/w 0 1: enable. 0: disable rcosc32k calibration . [0] wuc _ flag _ reset r/w 1: reset the wuc _ tmr_ prim _ toflag and wuc _ porflag bits (address 0x311, table 106 ). 0: normal operation . table 106 . 0x311: wuc _ status bit name r/w reset description [7] r eserved r 0 reserved . [6] wuc _ rcosc _ cal _ error r 0 1: rcosc32k calibration exited with error 0: without error (only valid if wuc _ rcosc _ cal _ en = 1) . [5] wuc _ rcosc _ cal _ ready r 0 1: rcosc32k calibration finished 0: in progress (only valid if wuc _ rcosc _ cal _ en = 1) . [4] xosc32k _ rdy r 0 1: xosc32k oscillator has settled 0: not settled (only valid if wuc _ xosc32k _ en = 1) . [3] xosc32k _ out r 0 output signal of the xosc32k oscillator (instantaneous) . [2] wuc _ porflag r 0 1: chip cold start event has been registered . 0: not registered . [1] wuc _ tmr_ prim _ toflag r 0 1: wuc timeout event has been registered . 0: not registered (the output of a latch triggered by a timeout event) . [0] wuc _ tmr_ prim _ toevent r 0 1: wuc timeout event is present . 0: not present (this bit is set when the counter reache s 0; it is not latched) . table 107 . 0x312: rssi _ readback bit name r/w reset description [7:0] rssi_ readback r 0 receive input power. after reception of a packet , the rssi_ readback value is valid. rssi (dbm) = rssi _ readback C 107 table 108 . 0x315: max _ afc _ range bit name r/w reset description [7:0] max _ afc _ range r/w 50 limits the afc pull - in range. automatically set by the communications processor on transitioning into the phy_rx state . the range is set equal to half the if bandwidth. example : if bandwidth = 200 khz, afc pull - in range = 100 khz (max_afc_range = 100) . table 109 . 0x319: image _ reject _ cal _ config bit name r/w reset description [7:6] r eserved r/w 0 [5] image _ reject _ c al _ ovwrt _ en r/w 0 overwrite control for image reject calibration results . [4:3] image _ reject _ frequency r/w 0 set the fundamental frequency of the ir calibration signal source . a harmonic of this frequency can be used as an int ernal rf signal source for the i mage rejection calibration . 0 : ir calibration source disabled in xtal divider 1 : ir calibration source fundamental frequency = xtal/ 4 2 : ir calibration source fundamental frequency = xtal/ 8 3 : ir calibration source fundamental frequency = xtal/16 [2:0] image _ reject _ power r/w 0 set power level of ir calibration source . 0 : ir calibration source disabled at mixer input 1 : power level = min 2 : power level = min 3 : power level = min 2 4 : power level = min 2 5 : power level = mi n 3 6 : power level = min 3 7 : power level = min 4
data sheet adf7023 rev. c | page 103 of 112 table 110 . 0x322: chip _ shutdown bit name r/w reset description [7: 1] r eserved r/w 0 [0] chip _ shtdn _ req r/w 0 wuc chip - state control flag. 0: remain in active state. 1: invoke chip shutdown. cs must also be high to initiate a shutdown. table 111 . 0x32 4 : powerdown_ rx bit name r/w reset description [7: 5] r eserved r/w 0 [4] adc_pd_n r/w 0 1: adc enabled 0: adc disabled [3] rssi_pd_n r/w 0 1: rssi enabled 0: rssi disabled [2] rxbbfilt_pd_n r/w 0 1: if f ilter enabled 0: if f ilter disabled [1] rxmixer_pd_n r/w 0 1: m ixer enabled 0: m ixer disabled [0] lna_pd_n r/w 0 1: lna enabled 0: lna disabled table 112 . 0x325: powerdown _ aux bit name r/w reset description [7:2] r eserved r/w 0 [1] tempmon _ pd_en r/w 0 1: enable 0: disable temperature monitor [0] battmon _ pd_ en r/w 0 1: enable 0: disable battery monitor table 113 . 0x327: adc _ readback _ high bit name r/w reset description [7:6 ] r eserved r 0 [5 :0] adc _ readback [7:2 ] r 0 adc readback of msbs table 114 . 0x328: adc _ readback _ low bit name r/w reset description [7:6 ] adc _ readback [1 :0] r 0 adc readback of lsbs [5 :0] r eserved r 0 table 115 . 0x32d: battery _ monitor _ threshold _ voltage bit name r/w reset description [7:5] r eserved r/w 0 [4:0] battmon _ v o ltage r/w 0 the b attery monitor threshold voltage sets the alarm level for the battery monitor. the alarm is raised by the interrupt. battery monitor trip voltage, v trip = 1.7 v + 62 mv bat tmon _ voltage . table 116 . 0x32e: ext _ uc _ clk _ divide bit name r/w reset description [7:4] r eserved r/w 0 [3:0] ext _ uc _ clk _ divide r/w 4 optional output clock frequency on xosc32kp_gp5 _atb1 . output f requency = xtal/ ext _ uc _ clk _ divide . to disable, set ext _ uc _ clk _ divide = 0.
adf7023 data sheet rev. c | page 104 of 112 table 117 . 0x32 f : agc _ clk _ divide bit name r/w reset description [ 7:0] agc _ clock _ divide r/w 40 agc clock d ivider for 2fsk/gfsk/msk/gmsk mode. the agc rate is (26 mhz /(16 agc _ clk _ divide )) . table 118 . 0x336: interrupt _ source _0 bit name r/w reset description [7] interrupt_num_wakeups r /w 0 asserted when the number of wuc wake - ups (number_of_wakeups[15:0]) has reached the threshold (number_of_wakeups_irq_threshold[15:0]) [6] interrupt_swm_rssi_det r /w 0 asserted when the measured rssi during smart wake mode has exceeded the rssi threshold value (s wm _rssi_thres h , address 0x108) [5] interrupt_aes_done r /w 0 asserted when an aes encryption or d ecryption command is complete; a vailable only when the aes firmware module has been loaded to the adf7023 program ram [4] interrupt_tx_eof r /w 0 asserted when a packet has finished transmitting (packet mode only) [3] interrupt_address_match r /w 0 asserted when a received packet has a valid address match (packet mode only) [2] interrupt_crc_correct r /w 0 asserted when a received packet has the correct crc (packet mode only) [1] interrupt_sync_detect r /w 0 asserted when a qualified sync word has been detected in the received packet [0] interrupt_preamble_detect r /w 0 asserted when a qualified preamble has been detected in the received packet table 119 . 0x337: interrupt _ source _1 bit name r/w reset description [7] bat tery _ alarm r/w 0 bat tery voltage dropped below the user - set threshold value. [6] cmd _ ready r/w 0 communications processor ready to accept a new command . [5] u nused r/w 0 [4] wuc _ timeout r/w 0 wake - up timer has timed out. [3] u nused r/w 0 [2] u nused r/w 0 [1] spi_ ready r/w 0 spi ready for access. [0] cmd_finished r/w 0 c ommand has finished. table 120 . 0x338: c alibration _c ontrol bit name r/w reset description [7:2] r eserved r/w 0 [1] synth _ cal _ en r/w 0 1: enable the synthesizer calibration state machine . 0: disable the synthesizer calibration state machine . [0] rxbb _ cal _ en r/w 0 1: enable receiver baseband filter (rxbb) calibration . 0: disable receiver baseband filter (rxbb) calibration . table 121 . 0x339: c alibration _s tatus bit name r/w reset description [7:3] r eserved r 0 [2] pa_ramp _ finished r 0 [1] synth _ cal _ ready r 0 1: synthesizer calibration finished successfully . 0: synthesizer calibration in progress . [0] rxbb _ cal _ ready r 0 receive if filter calibration . 1: complete . 0: in progress (valid while rxbb _ cal _ en = 1) .
data sheet adf7023 rev. c | page 105 of 112 table 122 . 0x345 : rxbb _ cal _ calwrd _ readback bit name r/w reset description [5:0] rxbb _ cal _ calwrd r 0 rxbb referen ce oscillator calibration word; valid after rxbb calibration cycle has been completed. table 123 . 0x346 : rxbb _ cal _ calwrd _ overwrite bit name r/w reset description [6:1] rxbb _ cal _ dcalwrd _ ovwrt _ in rw 0 rxbb reference oscill ator calibration overwrite word [0] rxbb _ cal _ dcalwrd _ ovwrt _ en rw 0 1: enable rxbb reference oscillator calibration word overwrite mod e 0 : disable rxbb reference oscillator calibration word overwrite mod e table 124 . 0x34f: rcosc_cal_readback_high bit name r/w reset description [7:0] rcosc_cal_readback[15:8] r 0x0 fine rc oscillator calibration result, b its[15:8] table 125 . 0x350: rcosc_cal_readback_low bit name r/w reset description [7:0] rcosc_cal_readback[7:0] r 0x0 fine rc oscillator calibration result, b its[7:0] table 126 . 0x359: adc _c onfig _l ow bit name r/w reset description [ 7:4 ] reserved r/w 0 set to 0. [3:2] adc _ ref _ chsel r/w 0 0: rssi (default) . 1 : external ain 2 : temperature sensor 3 : unused [1:0] adc _ reference _ control r/w 0 the following reference values are valid for a 3 v supply: 0 : 1.85 v (default) 1 : 1.95 v 2 : 1.75 v 3 : 1.65 v table 127 . 0x35a: adc _c onfig _h igh bit name r/w reset description [7] r eserved r/w 0 [6:5] filtered _ adc _ mode r/w 0 fi ltering modes . 00: normal operation (no filter) . 01: unfiltered agc loop, filtered readback (updated upon mcr read ). 10: unfiltered agc loop, filtered readback (update at agc clock rate) . 11: filtered agc loop, filtered readback . [4] adc _ ext _ ref _ enb r/w 1 bring low to power down t he adc reference . [3:0] r eserved r/w 1 set to 1 . table 128 . 0x35 b : agc _ ook_ control bit name r/w reset description [5:3] ook _ agc _ clk _ trk r/w 2 agc up date rate during tracking phase 1) ( 2 + = k_trk ook_age_cl man f rate update agc where f man = the m ancheste r symbol rate. manchester encoding is recommended for ook ; ook _ agc _ clk _ trk must be ook _ agc _ clk _ acq .
adf7023 data sheet rev. c | page 106 of 112 bit name r/w reset description [2:0] ook _ agc _ clk _ acq r/w 1 agc update rate during acquisition phase. 1)lk_acq (ook_age_c man f rate update agc + = 2 where f man = the m ancheste r symbol rate. manchester encoding is recommended for ook ; ook _ agc _ clk _ trk must be ook _ agc _ clk _ acq . table 129 . 0x35c : agc _ config bit name r/w reset description [7:6] lna _ gain _ change _ order r/w 2 lna gain change order [5:4] mixer _ gain _ change _ order r/w 1 mixer gain change order [3:2] filter _ gain _ change _ order r/w 3 filter gain change order [1] allow_extra _ lo _ lna_gain r/w 0 allow extra l ow lna gain setting [0] disallow _ max _ gain r/w 0 disallow max imum agc gain setting table 130 . 0x35d: agc _ mode bit name r/w reset description [7] r eserved r/w 0 [6:5] agc _ operation _ mcr r/w 0 0 : free - running agc 1 : manual agc 2 : hold agc 3 : lock agc after preamble [4:3] lna _ gain r/w 0 0 : low 1 : medium 2 : high 3 : reserved [2] mixer _ gain r/w 0 0: low 1: high [1:0] filter _ gain r/w 0 0: low 1 : medium 2 : high 3 : reserved table 131 . 0x3 5 e: agc _ low _ threshold bit name r/w reset description [ 7:0] agc _ low _ threshold r/w 55 agc low threshold table 132 . 0x3 5f : agc _ high _ threshold bit name r/w reset description [ 7:0] agc _ high _ threshold r/w 105 agc high threshold table 133 . 0x360: agc _ gain _ status bit name r/w reset description [7: 5] r eserved r 0 [4:3] lna _ gain _ readback r 0 0: low 1 : medium 2 : high 3 : reserved [2] mixer _ gain _ readback r 0 0: low 1: high [1:0] filter _ gain _ readback r 0 0 : low 1 : medium 2 : high 3 : reserved
data sheet adf7023 rev. c | page 107 of 112 table 134 . 0x361: agc_adc_word bit name r/w reset description [7 ] r eserved r 0 r eserved . [6 :0] agc_adc_word r 0 auxiliary adc sample word used when calculating rss i of ook signals. see the rssi method 4 section for more information. table 135 . 0x372: frequency _ error _ readback bit name r/w reset description [7:0] frequency _ error _ readback r 0 frequency error between received signal frequency and receive channel frequency = frequency _ error _ readback 1 khz. the frequency_error_readback value is in twos complement format . table 136 . 0x3cb : vco _ band _ ovrw _ val bit name r/w reset description [7:0] vco _ band _ ovrw _ val r/w 0 overwrite value for the vco frequency band; active when vco _ band _ ovrw _ en = 1 . table 137 . 0x3cc : vco _ ampl _ ovrw _ val bit name r/w reset description [7:0] vco _ ampl _ ovrw _ val r/w 0 overwrite value for the vco bias current dac; a ctive when vco _ ampl _ ovrw _ en = 1 . table 138 . 0x3cd : vco _ ovrw _ en bit name r/w reset description [7:6] r eserved r/w 0 r eserved . [5:2] vco_q_amp_ref r/w 0 vco amplitude level control reference dac during q phase. [1] vco _ ampl _ ovrw _ en r/w 0 1: e nable vco bias current dac overwrite . 0: d isable vco bias current dac overwrite . [0] vco _ band _ ovrw _ en r/w 0 1: e nable vco frequency band overwrite . 0: di sable vco frequency band overwrite . table 139 . 0x3d0 : vco _ cal _ cfg bit name r/w reset description [7:4] r eserved r/w 0 r eserved . [3:0] vco _ cal _ cfg r/w 1 vco calibration state machine configuration. set vco _ cal _ cfg = 0xf to bypass vco calibration on the phy_tx and phy_rx transitions. set vco _ cal _ cfg = 0x1 to enable the vco calibrations on the t ransitions . table 140 . 0x3d2 : osc_config bit name r/w reset description [7:6] r eserved r/w 0 write 0 . [5:3] xosc _ cap _ dac r/w 0 26 mhz crystal oscillator (xosc26n) tuning capacitor control word . [2:0] r eserved r/w 0 write 0 . table 141 . 0x3da : vco _ band _ readback bit name r/w reset description [7:0] vco _ band _ readback r 0 read back of the vco bias current dac after calibration table 142 . 0x3db: vco _ ampl _ readback bit name r/w reset description [7:0] vco _ ampl _ readback r 0 read back of the vco bias current dac after calibration table 143 . 0x3f8: analog _ test _ bus bit name r/w reset description [7:0] analog_test_bus r /w 0 to enable analog rssi on atb3 , set analog_test_bus = 0x64 in conjunction with setting rssi_ tstmux _ sel = 0x3.
adf7023 data sheet rev. c | page 108 of 112 table 144 . 0x3f9: rssi _ tstmux _ sel bit name r/w reset description [7] r eserved r/w 0 [6:2] r eserved r/w 0 [1:0] rssi_ tstmux _sel r/w 0 to enable analog rssi on atb3 , set rssi_ tstmux _sel = 0x3 in conjunction with setting analog_test_bus = 0x64 . table 145 . 0x3fa: gpio _ configure bit name r/w reset description [7:0] gpio _ configure r/w 0 0x00: default 0x21: s licer output on gp 5 ( that is, bypass cdr) 0x40: l imiter outputs on gp0(q) and gp1(i) 0x4 1 : f iltered l imiter outputs on gp0(q) and gp1(i) and un filtered limiter outputs on gp2(q) and irq_gp3 (i) 0x50: packet transmit data from communications processor on gp0 0x53: pa ramp finished on gp0 0xa0: sport m ode 0 0xa1 : sport m ode 1 0xa2 : sport m ode 2 0xa3 : sport m ode 3 0xa4 : sport m ode 4 0xa5 : sport m ode 5 0xa6 : sport m ode 6 0xa7: sport mode 7 0xa8: sport mode 8 0xc9: t est dac output on gp0 (also must set test_dac_gain) table 146 . 0x3fd: test _ dac _ gain bit name r/w reset description [ 7:4 ] r eserved r/w 0 r eserved . [3:0] test _ dac _ gain r/w 4 set test _ dac _ gain = 0 when using the test dac .
data sheet adf7023 rev. c | page 109 of 112 outline dimensions figure 117 . 32 - lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp - 32 - 13) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADF7023BCPZ ?40c to +85c 32 - lead lead frame chip scale package [lfcsp_wq] cp -32 -13 ADF7023BCPZ -rl ?40c to +85c 32 - lead lead frame chip scale package [lfcsp_wq] cp -32 -13 eval - adf7xxxmb3z evaluation board (usb motherb oard) eval - adf7023db1z evaluation board (rf daughterb oard , 868 mhz /915 mhz, separate match ) eval - adf7023db2z evaluation board (rf daughterb oard , 868 mhz /915 mhz, combined match ) eval - adf7023db3z evaluation board (rf daughterboard, 433 mhz, separate match) eval - adf7023db4z evaluation board (rf daughterboard, 433 mhz, combined match) 1 z = rohs compliant p art. 033009-a 1 0.50 bsc bot t om view top view pin 1 indic at or 32 9 16 17 24 25 8 exposed pa d pin 1 indic at or sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min 3.45 3.30 sq 3.15 compliant to jedec standards mo-220- whhd .
adf7023 rev. c | page 110 of 112 notes
data sheet adf7023 rev. c | page 111 of 112 notes
adf7023 rev. c | page 112 of 112 notes ? 2010 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08291 -0- 7/12(c)

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